On Mon, 23 Feb 2026 17:02:08 +0000 Peter Maydell <[email protected]> wrote:
> Advertise the GICv5 in the DTB. This binding is final as it is in > the upstream Linux kernel as: > Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml > > Signed-off-by: Peter Maydell <[email protected]> One trivial thing inline that might every so slightly help other reviewers. Otherwise looks correct to me - though take into account I only review this side of bindings once in a blue moon. Reviewed-by: Jonathan Cameron <[email protected]> > --- > hw/arm/virt.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index a9addf5ac0..6775062c5d 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -795,6 +795,72 @@ static void create_v2m(VirtMachineState *vms) > vms->msi_controller = VIRT_MSI_CTRL_GICV2M; > } > > +static void fdt_add_gicv5_node(VirtMachineState *vms) > +{ > + MachineState *ms = MACHINE(vms); > + const char *nodename = "/intc"; > + g_autofree char *irsnodename = NULL; > + g_autofree uint32_t *cpu_phandles = g_new(uint32_t, ms->smp.cpus); > + g_autofree uint16_t *iaffids = g_new(uint16_t, ms->smp.cpus); > + > + vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); > + qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", > vms->gic_phandle); > + > + qemu_fdt_add_subnode(ms->fdt, nodename); > + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); > + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "arm,gic-v5"); > + qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); > + qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); > + qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); > + qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); > + qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); > + > + /* The IRS node is a child of the top level /intc node */ > + irsnodename = g_strdup_printf("%s/irs@%" PRIx64, > + nodename, > + vms->memmap[VIRT_GICV5_IRS_NS].base); > + qemu_fdt_add_subnode(ms->fdt, irsnodename); > + qemu_fdt_setprop_string(ms->fdt, irsnodename, "compatible", > + "arm,gic-v5-irs"); > + /* > + * "reg-names" describes the frames whose address/size is in "reg"; > + * at the moment we have only the NS config register frame. > + */ > + qemu_fdt_setprop_string(ms->fdt, irsnodename, "reg-names", "ns-config"); Don't really care, but you could keep these ordered as per the binding doc to make review a tiny little bit easier. reg comes before reg-names. > + qemu_fdt_setprop_sized_cells(ms->fdt, irsnodename, "reg", > + 2, vms->memmap[VIRT_GICV5_IRS_NS].base, > + 2, vms->memmap[VIRT_GICV5_IRS_NS].size);
