On Tue, Mar 10, 2026 at 10:20 PM Brian Cain <[email protected]> wrote:
> Some of the system registers are shared among all threads > in the core. This object contains the representation and > interface to the system registers. > > Signed-off-by: Brian Cain <[email protected]> > --- > include/hw/hexagon/hexagon_globalreg.h | 56 ++++++ > hw/hexagon/hexagon_globalreg.c | 240 +++++++++++++++++++++++++ > 2 files changed, 296 insertions(+) > create mode 100644 include/hw/hexagon/hexagon_globalreg.h > create mode 100644 hw/hexagon/hexagon_globalreg.c > > diff --git a/include/hw/hexagon/hexagon_globalreg.h > b/include/hw/hexagon/hexagon_globalreg.h > new file mode 100644 > index 00000000000..c9e72f30b0a > --- /dev/null > +++ b/include/hw/hexagon/hexagon_globalreg.h > @@ -0,0 +1,56 @@ > +/* > + * Hexagon Global Registers QOM Object > + * > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef HEXAGON_GLOBALREG_H > +#define HEXAGON_GLOBALREG_H > + > +#include "hw/core/qdev.h" > +#include "hw/core/sysbus.h" > +#include "qom/object.h" > +#include "target/hexagon/cpu.h" > + > +#define TYPE_HEXAGON_GLOBALREG "hexagon-globalreg" > +OBJECT_DECLARE_SIMPLE_TYPE(HexagonGlobalRegState, HEXAGON_GLOBALREG) > + > +struct HexagonGlobalRegState { > + SysBusDevice parent_obj; > + > + /* Array of system registers */ > + uint32_t regs[NUM_SREGS]; > + > + /* Global performance cycle counter base */ > + uint64_t g_pcycle_base; > + > + /* Properties for global register reset values */ > + uint32_t boot_evb; /* Boot Exception Vector Base > (HEX_SREG_EVB) */ > + uint64_t config_table_addr; /* Configuration table base */ > + uint32_t dsp_rev; /* DSP revision register (HEX_SREG_REV) */ > + > + /* ISDB properties */ > + bool isdben_etm_enable; /* ISDB ETM enable bit */ > + bool isdben_dfd_enable; /* ISDB DFD enable bit */ > + bool isdben_trusted; /* ISDB trusted mode bit */ > + bool isdben_secure; /* ISDB secure mode bit */ > Should the TLB entries go in here also? > +}; > + > +/* Public interface functions */ > +uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg, > + uint32_t htid); > Why is htid needed? > +void hexagon_globalreg_write(HexagonGlobalRegState *s, uint32_t reg, > + uint32_t value, uint32_t htid); > Ditto > +uint32_t hexagon_globalreg_masked_value(HexagonGlobalRegState *s, > uint32_t reg, > + uint32_t value); > +void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t > reg, > + uint32_t value); > +void hexagon_globalreg_reset(HexagonGlobalRegState *s); > + > +/* Global performance cycle counter access */ > +uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s); > +void hexagon_globalreg_set_pcycle_base(HexagonGlobalRegState *s, > + uint64_t value); > + > +#endif /* HEXAGON_GLOBALREG_H */ > diff --git a/hw/hexagon/hexagon_globalreg.c > b/hw/hexagon/hexagon_globalreg.c > new file mode 100644 > index 00000000000..5187b91dcae > --- /dev/null > +++ b/hw/hexagon/hexagon_globalreg.c > @@ -0,0 +1,240 @@ > +static void hexagon_globalreg_init(Object *obj) > +{ > + HexagonGlobalRegState *s = HEXAGON_GLOBALREG(obj); > + > + memset(s->regs, 0, sizeof(uint32_t) * NUM_SREGS); > Should we memset the whole thing? > +} > >
