Rename target_get_monitor_def() as riscv_monitor_get_register_legacy() and register it as SysemuCPUOps::monitor_get_register() handler. Take care to sign-extend values for 32-bit HARTs.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Acked-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> --- target/riscv/internals.h | 3 +++ target/riscv/cpu.c | 1 + target/riscv/monitor.c | 11 +++++++---- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index bac6c8032a2..8c24af0d855 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -250,4 +250,7 @@ static inline int insn_len(uint16_t first_word) return (first_word & 3) == 3 ? 4 : 2; } +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, + int64_t *pval); + #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ce15a17c37d..a13727c0d4b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2733,6 +2733,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { .get_phys_page_debug = riscv_cpu_get_phys_page_debug, .write_elf64_note = riscv_cpu_write_elf64_note, .write_elf32_note = riscv_cpu_write_elf32_note, + .monitor_get_register = riscv_monitor_get_register_legacy, .legacy_vmsd = &vmstate_riscv_cpu, }; #endif diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index bca04a7580c..3898595a3cb 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -27,6 +27,7 @@ #include "monitor/hmp.h" #include "monitor/hmp-target.h" #include "system/memory.h" +#include "internals.h" #ifdef TARGET_RISCV64 #define PTE_HEADER_FIELDS "vaddr paddr "\ @@ -311,16 +312,18 @@ static bool reg_is_vreg(const char *name) return false; } -int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, + int64_t *pval) { - CPURISCVState *env = &RISCV_CPU(cs)->env; + RISCVCPU *hart = RISCV_CPU(cs); + CPURISCVState *env = cpu_env(cs); target_ulong val = 0; uint64_t val64 = 0; int i; if (reg_is_ulong_integer(env, name, &val, false) || reg_is_ulong_integer(env, name, &val, true)) { - *pval = val; + *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val; return 0; } @@ -369,7 +372,7 @@ int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) * to do the filtering of the registers that are present. */ if (res == RISCV_EXCP_NONE) { - *pval = val; + *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val; return 0; } } -- 2.53.0
