On Thu, May 07, 2026 at 01:57:02PM -0500, Andrew Jones wrote:
> On Thu, May 07, 2026 at 02:38:34PM +1000, Nicholas Piggin wrote:
> > Ascalon supports Svadu (hardware A/D bit updates).
> >
> > QEMU makes Svadu and Svade mutually exclusive, remove Svade so
> > Ascalon comes up with Svadu working.
>
> Hi Nicholas,
>
> Svadu and Svade aren't mutually exclusive, you can see the expected
> behaviors for the pair in the commit message of commit 70d22fd92c3b
> ("target/riscv: Gate hardware A/D PTE bit updating").
Okay misunderstood what QEMU is doing. What does it mean for an
implementation to support Svadu && !Svade? AFAIKS the spec says ADUE=0
means the access is performed as though Svade is implemented. I'm either
wrong about that or miss the point why Svadu && Svade is handled
differently in the patch you reference (or both).
> Does the
> Ascalon support Svade? If so, then it's probably best to enable both
> and leave it to Linux to enable Svadu with SBI FWFT
> SBI_FWFT_PTE_AD_HW_UPDATING in order to maximize the amount of
> software supported. But, unfortunately Linux doesn't yet support the
> checking for and enabling of SBI_FWFT_PTE_AD_HW_UPDATING. We still
> need kernel patches for that.
Our docs say it supports both. If enabling both bits is the correct
thing to do we should go with that for upstream.
Thanks,
Nick
