On 5/11/26 13:22, James Hilliard wrote:
+static void octeon_reset_mtm0_mpl_state(void)
+{
+ TCGv_i64 zero = tcg_constant_i64(0);
+
+ /*
+ * MTM0 defines MPL1 as zero; model the architecturally unpredictable
+ * MPL2/MPL4/MPL5 lanes as zero for deterministic emulation.
+ */
+ octeon_store_mpl(1, zero);
+ octeon_store_mpl(2, zero);
+ octeon_store_mpl(4, zero);
+ octeon_store_mpl(5, zero);
Where do you get that from?
The octeon2 documentation, which only has MPL[0-2], MTM0 does *not* modify either MPL1 or
MPL2. While I don't know what changed with octeon3, I really doubt this statement is
true. It just doesn't make any sense.
r~
