Hi Frank,
On 4/13/26 4:19 PM, Frank Chang wrote:
Hi Zhiwei,
LIU Zhiwei <[email protected]> 於 2026年4月9日週四 上午3:24寫道：
This patch completes the SMMPT implementation by adding support for the
new fence instructions: `mfence.spa` and `minval.spa`.
According to the specification, these instructions act as memory ordering
fences for MPT updates. In QEMU's TCG model, this is conservatively
implemented by flushing the entire TLB, which ensures that any subsequent
memory accesses will re-evaluate permissions and see the effects of any prior
MPT modifications.
The instructions are privileged and will cause an illegal instruction
exception if executed outside of M-mode.
Co-authored-by: Huang Tao <[email protected]>
Co-authored-by: TANG Tiancheng <[email protected]>
Signed-off-by: LIU Zhiwei <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
---
target/riscv/insn32.decode | 2 ++
.../riscv/insn_trans/trans_privileged.c.inc | 30 +++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6e35c4b1e6..84cec57daf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -120,6 +120,8 @@ sret 0001000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
+mfence_spa 1000011 ..... ..... 000 00000 1110011 @sfence_vma
+minval_spa 0000011 ..... ..... 000 00000 1110011 @sfence_vma
# *** NMI ***
mnret 0111000 00010 00000 000 00000 1110011
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
b/target/riscv/insn_trans/trans_privileged.c.inc
index 8a62b4cfcd..5ec6bf5991 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -160,3 +160,33 @@ static bool trans_sfence_vma(DisasContext *ctx,
arg_sfence_vma *a)
#endif
return false;
}
+
+#define REQUIRE_SMSDID(ctx) do { \
+ if (!ctx->cfg_ptr->ext_smsdid) { \
+ return false; \
+ } \
+} while (0)
+
+static bool do_mfence_spa(DisasContext *ctx)
+{
+#ifndef CONFIG_USER_ONLY
+ REQUIRE_SMSDID(ctx);
+ if (ctx->priv != PRV_M) {
+ return false;
+ }
+ decode_save_opc(ctx, 0);
+ gen_helper_tlb_flush_all(tcg_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_mfence_spa(DisasContext *ctx, arg_mfence_spa *a)
+{
+ return do_mfence_spa(ctx);
+}
+
+static bool trans_minval_spa(DisasContext *ctx, arg_minval_spa *a)
+{
+ return do_mfence_spa(ctx);
+}
The spec says that:
"When Svinval is implemented with Smsdid, the MINVAL.SPA instruction
must be implemented to
support such fine-granular invalidation of physical memory
access-permission caches."
I see it is just "when", not explicitly requires Svinval. Another reason
is that we implement minval.spa on QEMU in a not such fine-granular
invalidation way. Thus I don't make it require Svinval in v6 patch set.
If you have other comments, let me know.
Thanks,
Zhiwei
So I think we should call REQUIRE_SVINVAL() for MINVAL.SPA.
However, trans_privileged.c.inc is included before trans_svinval.c.inc.
So it might be better to separate these instructions into trans_smmpt.c.inc
and include it after trans_svinval.c.inc.
Regards,
Frank Chang
--
2.43.0
