Hi Rahul,
On 5/4/26 2:33 AM, Rahul Pathak wrote:
Hi Zhiwei
On Thu, Apr 9, 2026 at 12:55 AM LIU Zhiwei <[email protected]> wrote:
This patch completes the SMMPT implementation by adding support for the
new fence instructions: `mfence.spa` and `minval.spa`.
According to the specification, these instructions act as memory ordering
fences for MPT updates. In QEMU's TCG model, this is conservatively
implemented by flushing the entire TLB, which ensures that any subsequent
memory accesses will re-evaluate permissions and see the effects of any prior
MPT modifications.
The instructions are privileged and will cause an illegal instruction
exception if executed outside of M-mode.
Co-authored-by: Huang Tao <[email protected]>
Co-authored-by: TANG Tiancheng <[email protected]>
Signed-off-by: LIU Zhiwei <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
---
target/riscv/insn32.decode | 2 ++
.../riscv/insn_trans/trans_privileged.c.inc | 30 +++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6e35c4b1e6..84cec57daf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -120,6 +120,8 @@ sret 0001000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
+mfence_spa 1000011 ..... ..... 000 00000 1110011 @sfence_vma
+minval_spa 0000011 ..... ..... 000 00000 1110011 @sfence_vma
SMMTT spec version 0.49 mentions them as mfence.pa and minval.pa
This is still on v0.3.4. I still make it consistent in v6 patch set.
Maybe we can update to other new versions in the future.
Thanks,
Zhiwei
Thanks
Rahul
