Re: [PATCH v5 6/6] target/riscv: Enable SMMPT extension

[LIU Zhiwei]

Hi Daniel,

On 4/30/26 5:32 PM, Daniel Henrique Barboza wrote:

Hi Zhiwei,


It was brought to my attention that, as per spec 0.49, smmpt is dependent
on smsdid.  In other words, using our current implicit rules framework,
enabling smmpt would also enable smsdid.  I checked myself, and on
doc version 0.49, start of Chapter 4:

https://github.com/riscv/riscv-smmtt/releases/tag/v0.49

"The following MPT extensions are defined:

• Smmpt34 - Page-based 34-bit memory protection system (RV32 only)
• Smmpt43 - Page-based 43-bit memory protection system (RV64 only)
• Smmpt52 - Page-based 52-bit memory protection system (RV64 only)
• Smmpt64 - Page-based 64-bit memory protection system (RV64 only)

These MPT extensions depend on Smsdid. "


Given that a v6 is going to happen anyway might as well change this patch
to add this implicit rule too.

Yes. I have added this implicit rule in v6 patch set.

Thanks,
Zhiwei

Cheers,
Daniel


On 4/8/2026 11:06 AM, LIU Zhiwei wrote:

Co-authored-by: Huang Tao <eric.hu...@linux.alibaba.com>
Co-authored-by: TANG Tiancheng <lyn...@linux.alibaba.com>
Signed-off-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
---
  target/riscv/cpu.c | 4 ++++
  1 file changed, 4 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cb4ccd001d..1e49465eeb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -225,8 +225,10 @@ const RISCVIsaExtData isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
      ISA_EXT_DATA_ENTRY(smpmpmt, PRIV_VERSION_1_12_0, ext_smpmpmt),
      ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),
+    ISA_EXT_DATA_ENTRY(smmpt, PRIV_VERSION_1_13_0, ext_smmpt),
      ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm),
      ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
+    ISA_EXT_DATA_ENTRY(smsdid, PRIV_VERSION_1_13_0, ext_smsdid),
      ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
      ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
      ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg),

@@ -1379,6 +1381,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {

    /* These are experimental so mark with 'x-' */
  const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+    MULTI_EXT_CFG_BOOL("x-smmpt", ext_smmpt, false),
+    MULTI_EXT_CFG_BOOL("x-smsdid", ext_smsdid, false),
      MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
        { },