Hi Daniel,
On 5/11/26 5:29 PM, Daniel Henrique Barboza wrote:
Hi Zhiwei,
I was re-reading the code and the version history and I realized that
these patches seems to be based on version v0.34. At least this is
what is mentioned on the v1 cover:
"This patch set implements the v0.3.4 version of Smmpt"
(https://github.com/riscv/riscv-smmtt/releases/tag/v0.3.4).
https://lore.kernel.org/qemu-devel/[email protected]/
Seeing the changelog from 0.34 to the current version (0.49) there's
a lot of differences, including opcode values.
I think it's worth bumping the patches to the latest spec version in
v6. Even if v6 takes more time (there were some IOMPT register changes
that landed on v0.42). Latest version 0.49 is staled since January 26,
ratification target set to Q32026:
https://riscv.atlassian.net/browse/RVS-1345
Thus I think we're in good shape implementing v0.49 it without the
risk of
changing behind our backs.
As SMMPT extension have many other sub extensions, I'd like to submit
what we have now(aonther patch set about Smsdia is also depend on
v0.3.4) to make a base for future develop.
Thanks,
Zhiwei
Thanks,
Daniel
On 4/8/2026 11:06 AM, LIU Zhiwei wrote:
This patch set introduces support for the RISC-V Smmpt (Supervisor
Memory-tracking and Protection Table) extension. Smmpt provides a
hardware mechanism for fine-grained memory protection, checked after
address translation, which is particularly useful for supervisor-level
sandboxing and security monitoring.
The rfc patch set:
https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html
v4->v5:
1. Rebase to master.
v3->v4:
1. Add missing review tags.
v2->v3:
1. Fix build error in patch 2.
2. Rebase to master.
rfc->v2:
1. When ext_smmpt is false or BARE mode, make other fields in mmpt
CSR zero.
2. Add patch 5 to fix smrnmi ISA string order.
3. Fix patch 6 smmpt and smsdid ISA string order.
4. Make smmpt and smsdid experiment extensions.
5. Add review tags.
LIU Zhiwei (6):
target/riscv: Add basic definitions and CSRs for SMMPT
target/riscv: Implement core SMMPT lookup logic
target/riscv: Integrate SMMPT checks into MMU and TLB fill
target/riscv: Implement SMMPT fence instructions
target/riscv: Fix smrnmi isa alphabetical order
target/riscv: Enable SMMPT extension
target/riscv/cpu.c | 6 +-
target/riscv/cpu.h | 9 +-
target/riscv/cpu_bits.h | 27 ++
target/riscv/cpu_cfg_fields.h.inc | 2 +
target/riscv/cpu_helper.c | 81 +++++-
target/riscv/csr.c | 95 ++++++
target/riscv/insn32.decode | 2 +
.../riscv/insn_trans/trans_privileged.c.inc | 30 ++
target/riscv/meson.build | 1 +
target/riscv/pmp.h | 3 +
target/riscv/riscv_smmpt.c | 274 ++++++++++++++++++
target/riscv/riscv_smmpt.h | 36 +++
12 files changed, 560 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/riscv_smmpt.c
create mode 100644 target/riscv/riscv_smmpt.h
