On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé <[email protected]> wrote: > > aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only > CPU (Cortex-A35), only available in the 64-bit binary. > > If we build this file as common object, these SoCs become > available in both 32 and 64-bit binaries; however when running > the introspection test on the 32-bit binary, the init() method > tries to init the Cortex-A35 type -- although not realizing it > -- which is not available. This can be avoided by deferring the > CPU type initialization to the SoC DeviceRealize step (this is > safe because nothing uses the CPU type before, only the GIC > access them, just after their realization). > > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > ---
Reviewed-by: Manos Pitsidianakis <[email protected]> > hw/arm/aspeed_ast27x0.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c > index 87dcb82e1b0..e50125bfeec 100644 > --- a/hw/arm/aspeed_ast27x0.c > +++ b/hw/arm/aspeed_ast27x0.c > @@ -418,11 +418,6 @@ static void aspeed_soc_ast2700_init(Object *obj) > g_assert_not_reached(); > } > > - for (i = 0; i < sc->num_cpus; i++) { > - object_initialize_child(obj, "cpu[*]", &a->cpu[i], > - aspeed_soc_cpu_type(sc->valid_cpu_types)); > - } > - > object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); > > object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); > @@ -701,6 +696,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, > Error **errp) > > /* CPU */ > for (i = 0; i < sc->num_cpus; i++) { > + object_initialize_child(OBJECT(dev), "cpu[*]", &a->cpu[i], > + aspeed_soc_cpu_type(sc->valid_cpu_types)); > object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", > aspeed_calc_affinity(i), &error_abort); > > -- > 2.53.0 >
