On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé <[email protected]> wrote: > > Emphasis the IDAU interface is restricted to TCG by
Emphasis? > moving the header under target/arm/tcg/. Move the > definition to cpu-v7m.c which also contains v7/v8 > hardware (NVIC), keeping only CPU types in cpu32.c. > > Reviewed-by: Pierrick Bouvier <[email protected]> > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > --- Reviewed-by: Manos Pitsidianakis <[email protected]> > include/hw/arm/armv7m.h | 2 +- > include/hw/misc/tz-msc.h | 2 +- > target/arm/{ => tcg}/idau.h | 4 ++-- > hw/arm/armv7m.c | 2 +- > target/arm/cpu.c | 2 +- > target/arm/ptw.c | 2 +- > target/arm/tcg/cpu-v7m.c | 11 +++++++++++ > target/arm/tcg/cpu32.c | 8 -------- > 8 files changed, 18 insertions(+), 15 deletions(-) > rename target/arm/{ => tcg}/idau.h (97%) > > diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h > index 98ad08db036..70555962bb9 100644 > --- a/include/hw/arm/armv7m.h > +++ b/include/hw/arm/armv7m.h > @@ -13,7 +13,7 @@ > #include "hw/core/sysbus.h" > #include "hw/intc/armv7m_nvic.h" > #include "hw/misc/armv7m_ras.h" > -#include "target/arm/idau.h" > +#include "target/arm/tcg/idau.h" > #include "qom/object.h" > #include "hw/core/clock.h" > > diff --git a/include/hw/misc/tz-msc.h b/include/hw/misc/tz-msc.h > index 07112d8caa3..6cf4c6b09eb 100644 > --- a/include/hw/misc/tz-msc.h > +++ b/include/hw/misc/tz-msc.h > @@ -51,7 +51,7 @@ > #define TZ_MSC_H > > #include "hw/core/sysbus.h" > -#include "target/arm/idau.h" > +#include "target/arm/tcg/idau.h" > #include "qom/object.h" > > #define TYPE_TZ_MSC "tz-msc" > diff --git a/target/arm/idau.h b/target/arm/tcg/idau.h > similarity index 97% > rename from target/arm/idau.h > rename to target/arm/tcg/idau.h > index 0ef5251971d..e5736ad848d 100644 > --- a/target/arm/idau.h > +++ b/target/arm/tcg/idau.h > @@ -25,8 +25,8 @@ > * connected to the CPU using a link property. > */ > > -#ifndef TARGET_ARM_IDAU_H > -#define TARGET_ARM_IDAU_H > +#ifndef TARGET_ARM_TCG_IDAU_H > +#define TARGET_ARM_TCG_IDAU_H > > #include "qom/object.h" > > diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c > index a29eab6c915..68a1cbd6316 100644 > --- a/hw/arm/armv7m.c > +++ b/hw/arm/armv7m.c > @@ -20,7 +20,7 @@ > #include "qemu/error-report.h" > #include "qemu/module.h" > #include "qemu/log.h" > -#include "target/arm/idau.h" > +#include "target/arm/tcg/idau.h" > #include "target/arm/cpu.h" > #include "target/arm/cpu-features.h" > #include "target/arm/cpu-qom.h" > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 31e0a12a986..76f5909e902 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -24,7 +24,6 @@ > #include "qemu/log.h" > #include "exec/page-vary.h" > #include "system/whpx.h" > -#include "target/arm/idau.h" > #include "qemu/module.h" > #include "qapi/error.h" > #include "cpu.h" > @@ -42,6 +41,7 @@ > #include "hw/intc/arm_gicv5_stream.h" > #ifdef CONFIG_TCG > #include "hw/intc/armv7m_nvic.h" > +#include "target/arm/tcg/idau.h" > #endif /* CONFIG_TCG */ > #endif /* !CONFIG_USER_ONLY */ > #include "system/tcg.h" > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index 8706dd59dd6..a4842a4b62b 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -17,7 +17,7 @@ > #include "cpu.h" > #include "internals.h" > #include "cpu-features.h" > -#include "idau.h" > +#include "target/arm/tcg/idau.h" > > typedef struct S1Translate { > /* > diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c > index dc249ce1f14..02abd831e6a 100644 > --- a/target/arm/tcg/cpu-v7m.c > +++ b/target/arm/tcg/cpu-v7m.c > @@ -11,6 +11,7 @@ > #include "qemu/osdep.h" > #include "cpu.h" > #include "accel/tcg/cpu-ops.h" > +#include "target/arm/tcg/idau.h" > #include "internals.h" > > #if !defined(CONFIG_USER_ONLY) > @@ -40,6 +41,16 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int > interrupt_request) > return ret; > } > > +static const TypeInfo arm_v8m_types[] = { > + { > + .name = TYPE_IDAU_INTERFACE, > + .parent = TYPE_INTERFACE, > + .class_size = sizeof(IDAUInterfaceClass), > + } > +}; > + > +DEFINE_TYPES(arm_v8m_types) > + > #endif /* !CONFIG_USER_ONLY */ > > static void cortex_m0_initfn(Object *obj) > diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c > index 2127d456ad6..73d21c6cf7d 100644 > --- a/target/arm/tcg/cpu32.c > +++ b/target/arm/tcg/cpu32.c > @@ -12,7 +12,6 @@ > #include "cpu.h" > #include "accel/tcg/cpu-ops.h" > #include "internals.h" > -#include "target/arm/idau.h" > #if !defined(CONFIG_USER_ONLY) > #include "hw/core/boards.h" > #endif > @@ -899,17 +898,10 @@ static const ARMCPUInfo arm_tcg_cpus[] = { > #endif > }; > > -static const TypeInfo idau_interface_type_info = { > - .name = TYPE_IDAU_INTERFACE, > - .parent = TYPE_INTERFACE, > - .class_size = sizeof(IDAUInterfaceClass), > -}; > - > static void arm_tcg_cpu_register_types(void) > { > size_t i; > > - type_register_static(&idau_interface_type_info); > for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { > arm_cpu_register(&arm_tcg_cpus[i]); > } > -- > 2.53.0 >
