On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé <[email protected]> wrote: > > 32-bit ARM max CPU is a 'Cortex-A57 advertising none of the AArch64 > features'. Keep it as close as possible as the A57, by implementing > the debug ID registers, following the changes in aarch64_a57_initfn > added by commits 48eb3ae64b3 ("target-arm: Adjust debug ID registers > per-CPU") and 09754ca867f ("target/arm: Implement AArch32 DBGDEVID, > DBGDEVID1, DBGDEVID2"). > > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > ---
Reviewed-by: Manos Pitsidianakis <[email protected]> > target/arm/tcg/cpu32.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c > index cf643ce43b1..2e8afc28602 100644 > --- a/target/arm/tcg/cpu32.c > +++ b/target/arm/tcg/cpu32.c > @@ -755,6 +755,9 @@ static void arm_max_initfn(Object *obj) > SET_IDREG(isar, ID_ISAR4, 0x00011142); > SET_IDREG(isar, ID_ISAR5, 0x00011121); > SET_IDREG(isar, ID_ISAR6, 0); > + cpu->isar.dbgdidr = 0x3516d000; > + cpu->isar.dbgdevid = 0x01110f13; > + cpu->isar.dbgdevid1 = 0x2; > cpu->isar.reset_pmcr_el0 = 0x41013000; > SET_IDREG(isar, CLIDR, 0x0a200023); > /* 32KB L1 dcache */ > -- > 2.53.0 >
