On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé
<[email protected]> wrote:
>
> Rather than having the 32-bit 'max' CPU type defined in
> cpu32.c and the 64-bit counter part in cpu64.c, unify the
> code in a single place in cpu-max.c. Define stubs for
> aarch64_host_initfn() and aarch64_max_tcg_initfn() in the
> 32-bit binary.
>
> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
> ---

Reviewed-by: Manos Pitsidianakis <[email protected]>

>  target/arm/internals.h   |  1 +
>  target/arm/cpu-max.c     | 65 ++++++++++++++++++++++++++++++++++++++++
>  target/arm/cpu64.c       | 21 +------------
>  target/arm/tcg/cpu32.c   | 29 ------------------
>  target/arm/tcg/stubs32.c | 10 +++++++
>  5 files changed, 77 insertions(+), 49 deletions(-)
>
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index c95f3d63138..ccada1c9018 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1759,6 +1759,7 @@ void aarch64_add_pauth_properties(Object *obj);
>  void aarch64_add_sve_properties(Object *obj);
>  void aarch64_add_sme_properties(Object *obj);
>  void aarch64_aa32_a57_init(Object *obj, bool aa32_only);
> +void aarch64_host_initfn(Object *obj);
>
>  /* Return true if the gdbstub is presenting an AArch64 CPU */
>  static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
> diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
> index 6fc54ebe74e..8cf8edc6535 100644
> --- a/target/arm/cpu-max.c
> +++ b/target/arm/cpu-max.c
> @@ -8,7 +8,10 @@
>
>  #include "qemu/osdep.h"
>  #include "qemu/units.h"
> +#include "system/hw_accel.h"
>  #include "system/kvm.h"
> +#include "system/qtest.h"
> +#include "system/tcg.h"
>  #include "target/arm/internals.h"
>  #include "target/arm/cpregs.h"
>
> @@ -178,3 +181,65 @@ void aa32_max_features(ARMCPU *cpu)
>
>      FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
>  }
> +
> +/*
> + * -cpu max: a CPU with as many features enabled as our emulation supports.
> + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
> + * this only needs to handle 32 bits, and need not care about KVM.
> + */
> +static void cpu_max_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +#ifdef TARGET_AARCH64
> +    const bool aarch64_enabled = true;
> +#else
> +    const bool aarch64_enabled = false;
> +#endif /* !TARGET_AARCH64 */
> +
> +    if (hwaccel_enabled()) {
> +        assert(aarch64_enabled);
> +        /*
> +         * When hardware acceleration enabled, '-cpu max' is
> +         * identical to '-cpu host'
> +         */
> +        aarch64_host_initfn(obj);
> +        return;
> +    }
> +
> +    if (tcg_enabled() || qtest_enabled()) {
> +        aarch64_aa32_a57_init(obj, !aarch64_enabled);
> +    }
> +
> +    if (!aarch64_enabled) {
> +        aa32_max_features(cpu);
> +#ifdef CONFIG_USER_ONLY
> +        /*
> +         * Break with true ARMv8 and add back old-style VFP short-vector
> +         * support. Only do this for user-mode, where -cpu max is the 
> default,
> +         * so that older v6 and v7 programs are more likely to work without
> +         * adjustment.
> +         */
> +        cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
> +#endif
> +    } else if (tcg_enabled()) {
> +        assert(aarch64_enabled);
> +        /*
> +         * '-cpu max' for TCG: we currently do this as
> +         * "A57 with extra things"
> +         */
> +        aarch64_max_tcg_initfn(obj);
> +    }
> +}
> +
> +static const ARMCPUInfo arm_max_cpu = {
> +    .name = "max",
> +    .initfn = cpu_max_initfn,
> +};
> +
> +static void arm_max_cpu_register_types(void)
> +{
> +    arm_cpu_register(&arm_max_cpu);
> +}
> +
> +type_init(arm_max_cpu_register_types)
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 499d154dace..28167355773 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -791,7 +791,7 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cpu)
>  }
>  #endif
>
> -static void aarch64_host_initfn(Object *obj)
> +void aarch64_host_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
>
> @@ -818,28 +818,9 @@ static void aarch64_host_initfn(Object *obj)
>      }
>  }
>
> -static void aarch64_max_initfn(Object *obj)
> -{
> -    if (hwaccel_enabled()) {
> -        /* When hardware acceleration enabled, '-cpu max' is identical to 
> '-cpu host' */
> -        aarch64_host_initfn(obj);
> -        return;
> -    }
> -
> -    if (tcg_enabled() || qtest_enabled()) {
> -        aarch64_aa32_a57_init(obj, false);
> -    }
> -
> -    /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
> -    if (tcg_enabled()) {
> -        aarch64_max_tcg_initfn(obj);
> -    }
> -}
> -
>  static const ARMCPUInfo aarch64_cpus[] = {
>      { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
>      { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
> -    { .name = "max",                .initfn = aarch64_max_initfn },
>  #if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX)
>      { .name = "host",               .initfn = aarch64_host_initfn },
>  #endif
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index a2f730451fb..8220d785f5b 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -711,32 +711,6 @@ static void sa1110_initfn(Object *obj)
>      cpu->reset_sctlr = 0x00000070;
>  }
>
> -#ifndef TARGET_AARCH64
> -/*
> - * -cpu max: a CPU with as many features enabled as our emulation supports.
> - * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
> - * this only needs to handle 32 bits, and need not care about KVM.
> - */
> -static void arm_max_initfn(Object *obj)
> -{
> -    ARMCPU *cpu = ARM_CPU(obj);
> -
> -    /* Cortex-A57 advertising none of the aarch64 features */
> -    aarch64_aa32_a57_init(obj, true);
> -
> -    aa32_max_features(cpu);
> -
> -#ifdef CONFIG_USER_ONLY
> -    /*
> -     * Break with true ARMv8 and add back old-style VFP short-vector support.
> -     * Only do this for user-mode, where -cpu max is the default, so that
> -     * older v6 and v7 programs are more likely to work without adjustment.
> -     */
> -    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
> -#endif
> -}
> -#endif /* !TARGET_AARCH64 */
> -
>  static const ARMCPUInfo arm_tcg_cpus[] = {
>      { .name = "arm926",      .initfn = arm926_initfn },
>      { .name = "arm946",      .initfn = arm946_initfn },
> @@ -760,9 +734,6 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>      { .name = "ti925t",      .initfn = ti925t_initfn },
>      { .name = "sa1100",      .initfn = sa1100_initfn },
>      { .name = "sa1110",      .initfn = sa1110_initfn },
> -#ifndef TARGET_AARCH64
> -    { .name = "max",         .initfn = arm_max_initfn },
> -#endif
>  };
>
>  static void arm_tcg_cpu_register_types(void)
> diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c
> index 3945dc49e5e..78f819ef6ff 100644
> --- a/target/arm/tcg/stubs32.c
> +++ b/target/arm/tcg/stubs32.c
> @@ -22,3 +22,13 @@ void aarch64_translate_code(CPUState *cs, TranslationBlock 
> *tb,
>  {
>      g_assert_not_reached();
>  }
> +
> +void aarch64_host_initfn(Object *obj)
> +{
> +    g_assert_not_reached();
> +}
> +
> +void aarch64_max_tcg_initfn(Object *obj)
> +{
> +    g_assert_not_reached();
> +}
> --
> 2.53.0
>

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