On 5/13/26 6:33 PM, Shaju Abraham wrote:
> Introduce data-structures required for the ARM property layer. There are
> four classes of properties:
> STRING: Multi-bit fields with arch-defined named values, such as
> ("off", "aes", "pmull", ...).
when you say "arch defined named values", if we take for instance SHA2
field of ID_AA64ISAR0
+IDREG_FIELD_START(ID_AA64ISAR0, SHA2, 12, 4, LOWER, 0)
+IDREG_FIELD_ARCH_VAL(0b0000, "off")
+IDREG_FIELD_ARCH_VAL(0b0001, "sha256")
+IDREG_FIELD_ARCH_VAL(0b0010, "sha512")
+IDREG_FIELD_END(ID_AA64ISAR0, SHA2)
I don't see such string value in the ARM ARM:
0b0000 No SHA2 instructions implemented.
0b0001 Implements instructions: SHA256H, SHA256H2, SHA256SU0, and SHA256SU1.
0b0010 Implements instructions: • SHA256H, SHA256H2, SHA256SU0, and
SHA256SU1. • SHA512H, SHA512H2, SHA512SU0, and SHA512SU1.
Where did you get those arch defined strings? The only source I can see
is linux sysreg and I am not sure this can be used as a reference.
Looking at target/arm/cpu-idregs.h.inc
+IDREG_FIELD_START(ID_AA64ISAR0, TLB, 56, 4, LOWER, 0)
+IDREG_FIELD_ARCH_VAL(0b0000, "off")
+IDREG_FIELD_ARCH_VAL(0b0001, "os")
+IDREG_FIELD_ARCH_VAL(0b0010, "range")
+IDREG_FIELD_END(ID_AA64ISAR0, TLB)
it looks not straightforward to link with ARM ARM
TLB, bits [59:56] Indicates support for Outer Shareable and TLB range
maintenance instructions. The value of this field is an IMPLEMENTATION
DEFINED choice of: 0b0000 Outer Shareable and TLB range maintenance
instructions are not implemented. 0b0001 Outer Shareable TLB maintenance
instructions are implemented. 0b0010 Outer Shareable and TLB range
maintenance instructions are implemented. All other values are reserved.
FEAT_TLBIOS implements the functionality identified by the values 0b0001
and 0b0010. FEAT_TLBIRANGE implements the functionality identified by
the value 0b0010. From Armv8.4, the only permitted value is 0b0010.
Access to this field is RO
Thanks
Eric
> BOOLEAN: 1-bit fields.
> NUMERIC: Numeric values like cache geometry, debug counter widths, etc.
> FRACTIONAL: Paired (base, frac) fields exposed as a single "M.F" string
> (e.g., CSV2/CSV2_FRAC, MPAM/MPAM_FRAC, RAS/RAS_FRAC, NV/NV_FRAC).
>
> Co-authored-by: Khushit Shah <[email protected]>
> Signed-off-by: Shaju Abraham <[email protected]>
> ---
> target/arm/arm-cpu-props.h | 36 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 target/arm/arm-cpu-props.h
>
> diff --git a/target/arm/arm-cpu-props.h b/target/arm/arm-cpu-props.h
> new file mode 100644
> index 0000000000..1dc3786ea9
> --- /dev/null
> +++ b/target/arm/arm-cpu-props.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * ARM CPU feature properties.
> + *
> + * User-facing QOM properties that map to fields of the AArch64 ID
> + * registers described in cpu-idregs.inc.h.
> + *
> + */
> +
> +#ifndef ARM_CPU_PROPS_H
> +#define ARM_CPU_PROPS_H
> +
> +#include "cpu-idregs.h"
> +
> +typedef enum ArmCpuPropType {
> + ARM_PROP_STRING,
> + ARM_PROP_BOOLEAN,
> + ARM_PROP_NUMERIC,
> + ARM_PROP_FRACTIONAL,
> +} ArmCpuPropType;
> +
> +typedef struct ArmFracVal {
> + const char *name;
> + uint64_t base_val;
> + uint64_t frac_val;
> +} ArmFracVal;
> +
> +typedef struct ArmCpuPropDesc {
> + const char *name;
> + ArmCpuPropType type;
> + ArmFieldIdx base_field;
> + ArmFieldIdx frac_field;
> + const ArmFracVal *vals;
> +} ArmCpuPropDesc;
> +
> +#endif
