On Mon, May 18, 2026 at 1:43 AM Philippe Mathieu-Daudé <[email protected]> wrote: > > On 15/5/26 20:04, Anton Johansson wrote: > > Convert riscv_csr_[read|write]() into target_ulong angnostic CSR access > > functions that can be safely used from outside of target/ without > > knowledge of the target register size. Replace the 4 existing CSR > > accesses in hw/ and linux-user/. > > > > Signed-off-by: Anton Johansson <[email protected]> > > Reviewed-by: Pierrick Bouvier <[email protected]> > > --- > > target/riscv/cpu.h | 7 ++++++- > > target/riscv/csr.h | 13 ------------- > > hw/riscv/riscv_hart.c | 7 +++---- > > linux-user/riscv/signal.c | 5 +++-- > > target/riscv/csr.c | 17 +++++++++++++++++ > > 5 files changed, 29 insertions(+), 20 deletions(-) > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index eb18e1f59f..3352409676 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -903,7 +903,12 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); > > RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env); > > uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); > > > > -#include "target/riscv/csr.h" > > +/* > > + * Externally facing CSR access functions, wrappers around riscv_csr*(). > > Return: #RISCVException > > > + */ > > + > > +int riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val); > > +int riscv_csr_read_i64(CPURISCVState *env, int csrn, uint64_t *res); > > s/int/RISCVException/? > > > > > /* > > * The event id are encoded based on the encoding specified in the > > diff --git a/target/riscv/csr.h b/target/riscv/csr.h > > index fef3cd34cb..370da83a69 100644 > > --- a/target/riscv/csr.h > > +++ b/target/riscv/csr.h > > @@ -23,19 +23,6 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int > > csrno, > > target_ulong new_value, > > target_ulong write_mask); > > > > -static inline void riscv_csr_write(CPURISCVState *env, int csrno, > > - target_ulong val) > > -{ > > - riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, > > TARGET_LONG_BITS), 0); > > -} > > - > > -static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) > > -{ > > - target_ulong val = 0; > > - riscv_csrr(env, csrno, &val); > > - return val; > > -} > > - > > typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, > > int csrno); > > typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, > > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c > > index e675358e1a..d1c7188369 100644 > > --- a/hw/riscv/riscv_hart.c > > +++ b/hw/riscv/riscv_hart.c > > @@ -67,12 +67,11 @@ static void csr_call(char *cmd, uint64_t cpu_num, int > > csrno, uint64_t *val) > > RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num)); > > CPURISCVState *env = &cpu->env; > > > > - int ret = RISCV_EXCP_NONE; > > + RISCVException ret = RISCV_EXCP_NONE; > > if (strcmp(cmd, "get_csr") == 0) { > > - ret = riscv_csrr(env, csrno, (target_ulong *)val); > > + ret = riscv_csr_read_i64(env, csrno, val); > > } else if (strcmp(cmd, "set_csr") == 0) { > > - ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, > > - MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); > > + ret = riscv_csr_write_i64(env, csrno, *val); > > } > > > > g_assert(ret == RISCV_EXCP_NONE); > > diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c > > index 358fa1d82d..9d5ba300e4 100644 > > --- a/linux-user/riscv/signal.c > > +++ b/linux-user/riscv/signal.c > > @@ -90,7 +90,8 @@ static void setup_sigcontext(struct target_sigcontext > > *sc, CPURISCVState *env) > > __put_user(env->fpr[i], &sc->fpr[i]); > > } > > > > - uint32_t fcsr = riscv_csr_read(env, CSR_FCSR); > > + uint64_t fcsr; > > + riscv_csr_read_i64(env, CSR_FCSR, &fcsr); > > __put_user(fcsr, &sc->fcsr); > > } > > > > @@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, > > struct target_sigcontext *sc) > > > > uint32_t fcsr; > > __get_user(fcsr, &sc->fcsr); > > - riscv_csr_write(env, CSR_FCSR, fcsr); > > + riscv_csr_write_i64(env, CSR_FCSR, fcsr); > > } > > > > static void restore_ucontext(CPURISCVState *env, struct target_ucontext > > *uc) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 6cc3fcd4e3..3ffb56e938 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -5716,6 +5716,23 @@ RISCVException riscv_csrrw(CPURISCVState *env, int > > csrno, > > return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, > > ra); > > } > > > > +int riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val) > > +{ > > + RISCVException ret; > > + ret = riscv_csrrw(env, csrno, NULL, val, > > + MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); > > + return ret; > > (Directly return?) > > > +} > > + > > +int riscv_csr_read_i64(CPURISCVState *env, int csrno, uint64_t *res) > > +{ > > + RISCVException ret; > > + target_ulong val = 0; > > + ret = riscv_csrr(env, csrno, &val); > > + *res = val; > > Clever :)
With the comments addressed: Reviewed-by: Alistair Francis <[email protected]> Alistair > > > + return ret; > > +} > > + > > static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, > > Int128 *ret_value, > > Int128 new_value, > >
