On Tue, May 12, 2026 at 1:31 PM Daniel Henrique Barboza <[email protected]> wrote: > > We want to reduce the usage of the riscv_cpu_* arrays in > target/riscv/cpu.c, centering everything in isa_edata_arr[] instead, to > reduce data duplication and make our lives a bit easier when adding new > extensions. > > To do that we'll have to make isa_edata_arr[] do what the other arrays > are currently doing, not breaking existing semantics in the process. > The riscv_cpu_* arrays have a few exclusive uses: > > - set default extensions for rv32 and rv64; > - create user CPU properties; > - misc uses around tcg-cpu.c and kvm-cpu.c. > > We'll slowly make isa_edata_arr[] supersede these arrays. Start by > adding a new 'prop_name' field in RISCVIsaExtData. This field is needed > because not all extensions have properties and not all properties match > the riscv,isa string name. > > Create two additional macros and reclassify existing isa_edata_arr[] > entries as follows: > > - ISA_EXT_DATA_ENTRY creates an entry where prop_name == riscv,isa. > Most of our regular extensions fall into this category; > - ISA_EXPERIMENTAL_EXT_DATA_ENTRY: same as above but add a "x-" to the > prop name, i.e. prop_name == "x-" + riscv,isa; > - ISA_INTERNAL_EXT_DATA_ENTRY: used to declared internal extensions. By > 'internal' we mean users/management can't set them on or off. > > With these new macros we can start our simplification by changing > riscv-qmp-cmds to use isa_edata_arr[]. We'll just scroll through it > once and gather what we need. > > Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.c | 60 +++++++++++++++++++++++------------ > target/riscv/cpu.h | 1 + > target/riscv/riscv-qmp-cmds.c | 30 ++++-------------- > 3 files changed, 47 insertions(+), 44 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ee8f6e5296..42555cb28f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -97,8 +97,24 @@ static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, > const RISCVCPUConfig *src) > #include "cpu_cfg_fields.h.inc" > } > > +/* Use this for regular user facing extensions */ > #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ > - {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} > + {#_name, #_name, _min_ver, CPU_CFG_OFFSET(_prop)} > + > +/* > + * Same as above but for experimental extensions. We'll add a > + * "x-" right after "_name" when creating the user property. > + */ > +#define ISA_EXPERIMENTAL_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ > + {#_name, "x-" #_name, _min_ver, CPU_CFG_OFFSET(_prop)} > + > +/* > + * Internal extensions are extensions we will declare in the > + * riscv,isa DT but they don't have an user property, i.e. > + * users/management can't enable/disable them. > + */ > +#define ISA_INTERNAL_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ > + {#_name, NULL, _min_ver, CPU_CFG_OFFSET(_prop)} > > /* > * Here are the ordering rules of extension naming defined by RISC-V > @@ -121,13 +137,13 @@ static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, > const RISCVCPUConfig *src) > * instead. > */ > const RISCVIsaExtData isa_edata_arr[] = { > - ISA_EXT_DATA_ENTRY(zic64b, PRIV_VERSION_1_12_0, ext_zic64b), > + ISA_INTERNAL_EXT_DATA_ENTRY(zic64b, PRIV_VERSION_1_12_0, ext_zic64b), > ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), > ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), > ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), > - ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, has_priv_1_11), > - ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11), > - ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11), > + ISA_INTERNAL_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, > has_priv_1_11), > + ISA_INTERNAL_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11), > + ISA_INTERNAL_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11), > ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, ext_ziccrse), > ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp), > ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss), > @@ -141,7 +157,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zilsd, PRIV_VERSION_1_12_0, ext_zilsd), > ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop), > ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), > - ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12), > ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo), > ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha), > ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas), > @@ -211,13 +227,14 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug), > - ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), > - ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha), > - ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12), > - ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12), > - ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12), > - ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12), > - ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, > + has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha), > + ISA_INTERNAL_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, > has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, > has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, > has_priv_1_12), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg), > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > @@ -232,20 +249,21 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg), > - ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), > + ISA_INTERNAL_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > - ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, > + has_priv_1_12), > ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), > ISA_EXT_DATA_ENTRY(ssctr, PRIV_VERSION_1_12_0, ext_ssctr), > ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp), > ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), > ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm), > - ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), > - ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, > ext_ssstateen), > + ISA_INTERNAL_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, > has_priv_1_12), > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), > - ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), > - ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), > - ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_INTERNAL_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12), > ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm), > ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), > ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), > @@ -253,7 +271,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > ISA_EXT_DATA_ENTRY(svrsw60t59b, PRIV_VERSION_1_13_0, ext_svrsw60t59b), > - ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), > + ISA_EXPERIMENTAL_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), > ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), > ISA_EXT_DATA_ENTRY(xlrbr, PRIV_VERSION_1_13_0, ext_xlrbr), > ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 224c81900d..669735c5cd 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -996,6 +996,7 @@ extern const RISCVCPUMultiExtConfig > riscv_cpu_named_features[]; > > typedef struct isa_ext_data { > const char *name; > + const char *prop_name; > int min_version; > int ext_enable_offset; > } RISCVIsaExtData; > diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c > index 8a1856c50e..93e6b7fa68 100644 > --- a/target/riscv/riscv-qmp-cmds.c > +++ b/target/riscv/riscv-qmp-cmds.c > @@ -90,27 +90,14 @@ static void riscv_obj_add_qdict_prop(Object *obj, QDict > *qdict_out, > } > } > > -static void riscv_obj_add_multiext_props(Object *obj, QDict *qdict_out, > - const RISCVCPUMultiExtConfig *arr) > +static void riscv_obj_add_multiext_props(Object *obj, QDict *qdict_out) > { > - for (int i = 0; arr[i].name != NULL; i++) { > - riscv_obj_add_qdict_prop(obj, qdict_out, arr[i].name); > - } > -} > + const RISCVIsaExtData *edata; > > -static void riscv_obj_add_named_feats_qdict(Object *obj, QDict *qdict_out) > -{ > - const RISCVCPUMultiExtConfig *named_cfg; > - RISCVCPU *cpu = RISCV_CPU(obj); > - QObject *value; > - bool flag_val; > - > - for (int i = 0; riscv_cpu_named_features[i].name != NULL; i++) { > - named_cfg = &riscv_cpu_named_features[i]; > - flag_val = isa_ext_is_enabled(cpu, named_cfg->offset); > - value = QOBJECT(qbool_from_bool(flag_val)); > - > - qdict_put_obj(qdict_out, named_cfg->name, value); > + for (edata = isa_edata_arr; edata && edata->name; edata++) { > + if (edata->prop_name) { > + riscv_obj_add_qdict_prop(obj, qdict_out, edata->prop_name); > + } > } > } > > @@ -220,10 +207,7 @@ CpuModelExpansionInfo > *qmp_query_cpu_model_expansion(CpuModelExpansionType type, > > qdict_out = qdict_new(); > > - riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_extensions); > - riscv_obj_add_multiext_props(obj, qdict_out, > riscv_cpu_experimental_exts); > - riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts); > - riscv_obj_add_named_feats_qdict(obj, qdict_out); > + riscv_obj_add_multiext_props(obj, qdict_out); > riscv_obj_add_profiles_qdict(obj, qdict_out); > > /* Add our CPU boolean options too */ > -- > 2.43.0 > >
