On Tue, May 12, 2026 at 1:31 PM Daniel Henrique Barboza <[email protected]> wrote: > > Deprecate riscv_cpu_enable_named_feat() by creating implied rules for > 'sha' and 'ssstateen'. 'zic64' is always true given that our default > block size is set to 64. > > With this change we homogeneize extension handling when enabling > profiles. > > Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.c | 25 ++++++++++++++++++++++-- > target/riscv/tcg/tcg-cpu.c | 40 -------------------------------------- > 2 files changed, 23 insertions(+), 42 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 42555cb28f..047f81b163 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2595,6 +2595,17 @@ static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = { > }, > }; > > +static RISCVCPUImpliedExtsRule SHA_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_sha), > + .implied_misa_exts = RVH, > + .implied_multi_exts = { > + CPU_CFG_OFFSET(ext_smstateen), > + CPU_CFG_OFFSET(ext_ssstateen), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > static RISCVCPUImpliedExtsRule SSCFG_IMPLIED = { > .ext = CPU_CFG_OFFSET(ext_ssccfg), > .implied_multi_exts = { > @@ -2643,6 +2654,15 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = { > }, > }; > > +static RISCVCPUImpliedExtsRule SSSTATEEN_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_ssstateen), > + .implied_multi_exts = { > + CPU_CFG_OFFSET(ext_smstateen), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = { > .ext = CPU_CFG_OFFSET(ext_zvfbfa), > .implied_multi_exts = { > @@ -2669,8 +2689,9 @@ RISCVCPUImpliedExtsRule > *riscv_multi_ext_implied_rules[] = { > &ZVFBFA_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, > &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, > &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, > - &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, > - &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, &SSCTR_IMPLIED, > + &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SHA_IMPLIED, > + &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, > + &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED, > NULL > }; > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 704105d3df..c3e354b0ae 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -322,42 +322,6 @@ static const char *cpu_cfg_ext_get_name(uint32_t > ext_offset) > g_assert_not_reached(); > } > > -static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) > -{ > - const RISCVCPUMultiExtConfig *feat; > - > - for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { > - if (feat->offset == ext_offset) { > - return true; > - } > - } > - > - return false; > -} > - > -static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) > -{ > - /* > - * All other named features are already enabled > - * in riscv_tcg_cpu_instance_init(). > - */ > - switch (feat_offset) { > - case CPU_CFG_OFFSET(ext_zic64b): > - cpu->cfg.cbom_blocksize = 64; > - cpu->cfg.cbop_blocksize = 64; > - cpu->cfg.cboz_blocksize = 64; > - break; > - case CPU_CFG_OFFSET(ext_sha): > - if (!cpu_misa_ext_is_user_set(RVH)) { > - riscv_cpu_write_misa_bit(cpu, RVH, true); > - } > - /* fallthrough */ > - case CPU_CFG_OFFSET(ext_ssstateen): > - cpu->cfg.ext_smstateen = true; > - break; > - } > -} > - > static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, > uint32_t ext_offset) > { > @@ -1327,10 +1291,6 @@ static void riscv_cpu_set_profile(RISCVCPU *cpu, > ext_offset = profile->ext_offsets[i]; > > if (profile->enabled) { > - if (cpu_cfg_offset_is_named_feat(ext_offset)) { > - riscv_cpu_enable_named_feat(cpu, ext_offset); > - } > - > cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); > } > > -- > 2.43.0 > >
