On Tue, May 12, 2026 at 1:32 PM Daniel Henrique Barboza <[email protected]> wrote: > > This array has no uses left. > > Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.c | 26 -------------------------- > target/riscv/cpu.h | 1 - > target/riscv/tcg/tcg-cpu.c | 4 ++-- > 3 files changed, 2 insertions(+), 29 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 047f81b163..4940596ffa 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1407,32 +1407,6 @@ const RISCVCPUMultiExtConfig > riscv_cpu_experimental_exts[] = { > { }, > }; > > -/* > - * 'Named features' is the name we give to extensions that we > - * don't want to expose to users. They are either immutable > - * (always enabled/disable) or they'll vary depending on > - * the resulting CPU state. > - * > - * Some of them are always enabled depending on priv version > - * of the CPU and are declared directly in isa_edata_arr[]. > - * The ones listed here have special checks during finalize() > - * time and require their own flags like regular extensions. > - * See riscv_cpu_update_named_features() for more info. > - */ > -const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { > - MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), > - MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true), > - MULTI_EXT_CFG_BOOL("sha", ext_sha, true), > - > - /* > - * 'ziccrse' has its own flag because the KVM driver > - * wants to enable/disable it on its own accord. > - */ > - MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true), > - > - { }, > -}; > - > static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname, > Error **errp) > { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 669735c5cd..46bc29d307 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -992,7 +992,6 @@ typedef struct RISCVCPUMultiExtConfig { > extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; > extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; > extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; > -extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; > > typedef struct isa_ext_data { > const char *name; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index c3e354b0ae..8dea22bae5 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -454,7 +454,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU > *cpu) > } > } > > -static void riscv_cpu_update_named_features(RISCVCPU *cpu) > +static void riscv_cpu_update_cfg(RISCVCPU *cpu) > { > if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { > cpu->cfg.has_priv_1_11 = true; > @@ -1181,7 +1181,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, > Error **errp) > return; > } > > - riscv_cpu_update_named_features(cpu); > + riscv_cpu_update_cfg(cpu); > riscv_cpu_validate_profiles(cpu); > > if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { > -- > 2.43.0 > >
