Dear all, Thanks for your review comments. I am currently occupied with another high priority task at the moment. Shall get back to addressing the review comments by mid June. Hence, please expect delay in response.
Regards. Saif On 05-03-2026 11:39, Saif Abrar wrote:
Hello, This patchset v4 resolves the tsan build failure seen in https://gitlab.com/mstredhat/qemu/-/jobs/13201554945 Few variables were declared directly after a case label inside a switch, causing the compilation failure. These are now moved to the top of the block. This series updates the existing PHB4 model to the latest spec: "Power Systems Host Bridge 5 (PHB5) Functional Specification Version 0.5_00". Updates include the following: - implemented sticky reset logic - implemented read-only, write-only, W1C and WxC logic - return all 1's on read to unimplemented registers - update PCIE registers for link status, speed and width - implement IODA PCT debug table without any functionality - update LSI Source-ID register based on small/big PHB number of interrupts Also, a new testbench for PHB4 model is added that does XSCOM read/writes to various registers of interest and verifies the values. Regards. Saif Abrar (9): qtest/phb4: Add testbench for PHB4 pnv/phb4: Add reset logic to PHB4 pnv/phb4: Implement sticky reset logic in PHB4 pnv/phb4: Implement read-only and write-only bits of registers pnv/phb4: Implement write-clear and return 1's on unimplemented reg read pnv/phb4: Set link-active status in HPSTAT and LMR registers pnv/phb4: Set link speed and width in the DLP training control register pnv/phb4: Implement IODA PCT table pnv/phb4: Mask off LSI Source-ID based on number of interrupts hw/pci-host/pnv_phb.c | 1 + hw/pci-host/pnv_phb4.c | 581 +++++++++++++++++++++++++--- include/hw/pci-host/pnv_phb4.h | 16 +- include/hw/pci-host/pnv_phb4_regs.h | 66 +++- tests/qtest/meson.build | 1 + tests/qtest/pnv-phb4-test.c | 228 +++++++++++ 6 files changed, 835 insertions(+), 58 deletions(-) create mode 100644 tests/qtest/pnv-phb4-test.c
