Add the common state needed by Octeon's selector-driven COP2 crypto interfaces. This includes storage for the base hash, AES, CRC, GFM, 3DES, KASUMI, and SNOW3G engines, plus the shared selector-window mode used by overlapping hardware register banks.
Describe the shared HSH/SHA512, SHA3, SNOW3G, and ZUC selector window up front so later engine patches can add their own state and helper logic without rewriting common comments. Keep selector values out of the CPU state header; decodetree owns instruction decode and helper-local constants cover the few shared-window arithmetic cases. Migrate the state in an Octeon-only subsection so non-Octeon CPU models do not grow migration data. Later patches wire helpers and explicit selector decode on top of this state. Signed-off-by: James Hilliard <[email protected]> --- Changes v8 -> v9: - Remove the MIPSOcteonCop2Sel enum; selector values are decoded by decodetree or kept local to helper plumbing. - Leave only COP2 state and migration data in this patch. Changes v7 -> v8: - Split COP2 crypto state and migration coverage out of the combined COP2 crypto core patch. --- target/mips/cpu.h | 37 +++++++++++++++++++++++++++++++++++++ target/mips/system/machine.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 346713705a..66c8653211 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -537,6 +537,41 @@ struct TCState { }; struct MIPSITUState; +typedef enum MIPSOcteonSharedMode { + OCTEON_SHARED_MODE_NONE = 0, + OCTEON_SHARED_MODE_SHA512, + OCTEON_SHARED_MODE_SNOW3G, +} MIPSOcteonSharedMode; + +typedef struct MIPSOcteonCryptoState { + uint64_t des3_key[3]; + uint64_t des3_iv; + uint64_t des3_result; + uint64_t hsh_iv[4]; + uint64_t hsh_dat[8]; + uint64_t hsh_ivw[8]; + uint64_t hsh_datw[16]; + uint64_t aes_iv[2]; + uint64_t aes_key[4]; + uint64_t aes_result[2]; + uint64_t aes_input[2]; + uint64_t gfm_mul[2]; + uint64_t gfm_resinp[2]; + uint64_t gfm_xor0; + uint64_t gfm_reflect_mul[2]; + uint64_t gfm_reflect_resinp[2]; + uint64_t gfm_reflect_xor0; + uint16_t gfm_poly; + uint8_t aes_keylen; + uint32_t shared_mode; + uint32_t crc_poly; + uint32_t crc_iv; + uint32_t crc_len; + uint32_t snow3g_fsm[3]; + uint32_t snow3g_lfsr[16]; + uint64_t snow3g_result; +} MIPSOcteonCryptoState; + typedef struct CPUArchState { TCState active_tc; CPUMIPSFPUContext active_fpu; @@ -558,6 +593,8 @@ typedef struct CPUArchState { #define MSAIR_ProcID 8 #define MSAIR_Rev 0 + MIPSOcteonCryptoState octeon_crypto; + /* * CP0 Register 0 */ diff --git a/target/mips/system/machine.c b/target/mips/system/machine.c index f988b3695b..ebfa0a9eb0 100644 --- a/target/mips/system/machine.c +++ b/target/mips/system/machine.c @@ -279,6 +279,42 @@ static const VMStateDescription mips_vmstate_octeon_multiplier = { } }; +static const VMStateDescription mips_vmstate_octeon_crypto = { + .name = "cpu/octeon_crypto", + .version_id = 1, + .minimum_version_id = 1, + .needed = mips_octeon_needed, + .fields = (const VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.octeon_crypto.des3_key, MIPSCPU, 3), + VMSTATE_UINT64(env.octeon_crypto.des3_iv, MIPSCPU), + VMSTATE_UINT64(env.octeon_crypto.des3_result, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_iv, MIPSCPU, 4), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_dat, MIPSCPU, 8), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_ivw, MIPSCPU, 8), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_datw, MIPSCPU, 16), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_iv, MIPSCPU, 2), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_key, MIPSCPU, 4), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_result, MIPSCPU, 2), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_input, MIPSCPU, 2), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_mul, MIPSCPU, 2), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_resinp, MIPSCPU, 2), + VMSTATE_UINT64(env.octeon_crypto.gfm_xor0, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_reflect_mul, MIPSCPU, 2), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_reflect_resinp, MIPSCPU, 2), + VMSTATE_UINT64(env.octeon_crypto.gfm_reflect_xor0, MIPSCPU), + VMSTATE_UINT16(env.octeon_crypto.gfm_poly, MIPSCPU), + VMSTATE_UINT8(env.octeon_crypto.aes_keylen, MIPSCPU), + VMSTATE_UINT32(env.octeon_crypto.shared_mode, MIPSCPU), + VMSTATE_UINT32(env.octeon_crypto.crc_poly, MIPSCPU), + VMSTATE_UINT32(env.octeon_crypto.crc_iv, MIPSCPU), + VMSTATE_UINT32(env.octeon_crypto.crc_len, MIPSCPU), + VMSTATE_UINT32_ARRAY(env.octeon_crypto.snow3g_fsm, MIPSCPU, 3), + VMSTATE_UINT32_ARRAY(env.octeon_crypto.snow3g_lfsr, MIPSCPU, 16), + VMSTATE_UINT64(env.octeon_crypto.snow3g_result, MIPSCPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_mips_cpu = { .name = "cpu", .version_id = 21, @@ -396,6 +432,7 @@ const VMStateDescription vmstate_mips_cpu = { .subsections = (const VMStateDescription * const []) { &mips_vmstate_timer, &mips_vmstate_octeon_multiplier, + &mips_vmstate_octeon_crypto, NULL } }; -- 2.54.0
