On 5/19/26 09:22, James Hilliard wrote:
Add helper support for the Octeon AES operation selectors. The direct
register-transfer selectors are handled later by the explicit decode
patch; this patch adds the ECB/CBC encrypt and decrypt operations that
consume the AES input, key, IV, and key-length state.
The AESRESINP direct write path keeps a separate input latch and readback
view. Later translator comments document that split where the direct TCG
stores are emitted.
Signed-off-by: James Hilliard <[email protected]>
---
Changes v8 -> v9:
- Split AES operation selectors into their own COP2 helper patch.
- Replace generic selector dispatch with per-operation AES helpers.
- Add matching helper.h declarations with the helper implementation.
---
target/mips/cpu.h | 5 ++
target/mips/helper.h | 4 ++
target/mips/tcg/octeon_crypto.c | 141 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 150 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b57a7a0584..801893b67f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -556,6 +556,11 @@ typedef struct MIPSOcteonCryptoState {
uint64_t sha3_state[25];
uint64_t aes_iv[2];
uint64_t aes_key[4];
+ /*
+ * AESRESINP is one architectural selector bank. Keep a separate input
+ * latch so operation selectors can consume a pending block while DMFC2
+ * reads expose the latest result/readback value.
+ */
uint64_t aes_result[2];
uint64_t aes_input[2];
Specific example? Because this seems wrong to me.
@@ -763,6 +763,116 @@ static void octeon_snow3g_more(MIPSOcteonCryptoState
*crypto)
octeon_set_shared_mode(crypto, OCTEON_SHARED_MODE_SNOW3G);
octeon_snow3g_queue_result(crypto);
}
+static int octeon_aes_key_bits(const MIPSOcteonCryptoState *crypto)
Missing newline, multiple instances.
Otherwise the actual operations look fine.
r~
