BADDU and DMUL write their results to rd, not rt. Route writes through gen_store_gpr() so rd == $zero is handled consistently.
Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: James Hilliard <[email protected]> --- Changes v1 -> v2: - Split the BADDU/DMUL destination handling fix out of the Octeon arithmetic instruction patch. (suggested by Philippe Mathieu-Daudé) Changes v2 -> v3: - Remove the rd == $zero fast paths and let gen_store_gpr() discard writes to $zero. (suggested by Richard Henderson) --- target/mips/tcg/octeon_translate.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index e1f52d444a..4dd7626835 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -45,18 +45,14 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a) { TCGv_i64 t0, t1; - if (a->rt == 0) { - /* nop */ - return true; - } - t0 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); gen_load_gpr(t1, a->rt); tcg_gen_add_i64(t0, t0, t1); - tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); + tcg_gen_andi_i64(t0, t0, 0xff); + gen_store_gpr(t0, a->rd); return true; } @@ -64,17 +60,13 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a) { TCGv_i64 t0, t1; - if (a->rt == 0) { - /* nop */ - return true; - } - t0 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); gen_load_gpr(t1, a->rt); - tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1); + tcg_gen_mul_i64(t0, t0, t1); + gen_store_gpr(t0, a->rd); return true; } -- 2.54.0
