VMM0 multiplies MPL[0] by rs, adds rt and the queued P[0] partial product, returns the low result, and feeds that result back into MPL[0]. It sets MPL[1] to zero and clears partial products.
Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: James Hilliard <[email protected]> Signed-off-by: Richard Henderson <[email protected]> --- Changes v8 -> v9: - Reuse octeon_zero_partial_product_state() for partial-product clearing. Changes v2 -> v3: - Split VMM0 out of the combined Octeon arithmetic and memory instruction patch. (requested by Richard Henderson) Changes v3 -> v4: - Document the Octeon3 chain update behavior. Changes v5 -> v6: - Zero MPL1 after checking the CN71XX VMM0 definition and add MPL1 smoke coverage. Changes v7 -> v8: - Use Richard Henderson's v7.5 inline TCG translator, which keeps only the architecturally defined MPL1 and partial-product clearing. --- target/mips/tcg/octeon.decode | 1 + target/mips/tcg/octeon_translate.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 36ced0bb33..f9c32e1dee 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -56,6 +56,7 @@ MTP1 011100 ..... ..... 00000 00000 001010 @r2 MTP2 011100 ..... ..... 00000 00000 001011 @r2 VMULU 011100 ..... ..... ..... 00000 001111 @r3 +VMM0 011100 ..... ..... ..... 00000 010000 @r3 &saa base rt @saa ...... base:5 rt:5 ................ &saa diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index 3216f2b2eb..10fd4e9ab2 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -300,3 +300,19 @@ static bool trans_VMULU(DisasContext *ctx, arg_VMULU *a) gen_store_gpr(tmp, a->rd); return true; } + +static bool trans_VMM0(DisasContext *ctx, arg_VMM0 *a) +{ + TCGv_i64 tmp = tcg_temp_new_i64(); + + gen_load_gpr(tmp, a->rs); + tcg_gen_mul_i64(oct_mpl[0], oct_mpl[0], tmp); + gen_load_gpr(tmp, a->rt); + tcg_gen_add_i64(oct_mpl[0], oct_mpl[0], tmp); + tcg_gen_add_i64(oct_mpl[0], oct_mpl[0], oct_p[0]); + gen_store_gpr(oct_mpl[0], a->rd); + + tcg_gen_movi_i64(oct_mpl[1], 0); + octeon_zero_partial_product_state(); + return true; +} -- 2.54.0
