On 19/5/26 18:22, James Hilliard wrote:
Octeon68XX cores implement CP1. Advertise that in the CPU definition by
setting Config1.FP, enabling the writable Status bits, and providing the
FCR0/FCR31 defaults used by this CPU model.
This lets guests observe the expected floating-point feature bits and use
CP1 with -cpu Octeon68XX.
Signed-off-by: James Hilliard <[email protected]>
---
Changes v1 -> v2:
- Move this CPU-model correction into a separate final patch.
(suggested by Philippe Mathieu-Daudé)
---
target/mips/cpu-defs.c.inc | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
Tested-by: Philippe Mathieu-Daudé <[email protected]>
