From: Amit Machhiwal <[email protected]>
Move the below instructions to decodetree specification:
s{r,l}d, and srad[i] : X-form
The changes were verified by validating that the TCG ops generated by
these instructions remain the same after these changes. The TCG
micro-ops were captured with the '-d op,in_asm' QEMU flag.
Move all shift insntructions to one place in insn32.decode
Signed-off-by: Sathvika Vasireddy <[email protected]>
Signed-off-by: Amit Machhiwal <[email protected]>
Signed-off-by: Chinmay Rath <[email protected]>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 11 ++-
target/ppc/int_helper.c | 2 +-
target/ppc/translate.c | 96 ----------------------
target/ppc/translate/fixedpoint-impl.c.inc | 72 ++++++++++++++++
5 files changed, 81 insertions(+), 102 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index d5283344ba..f267c0d2b8 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -75,7 +75,7 @@ DEF_HELPER_FLAGS_1(CBCDTD, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(CMPEQB, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(POPCNTW, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(BPERMD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_3(srad, tl, env, tl, tl)
+DEF_HELPER_3(SRAD, tl, env, tl, tl)
DEF_HELPER_FLAGS_0(DARN32, TCG_CALL_NO_RWG, tl)
DEF_HELPER_FLAGS_0(DARN64, TCG_CALL_NO_RWG, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index db6e9418f3..44ef814fb9 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -119,7 +119,7 @@
# XS-form with fractured shift amount
%xs_sh 1:1 11:5
-&XS rs ra sh rc
+&XS rs ra sh rc:bool
@XS ...... rs:5 ra:5 ..... ......... . rc:1 &XS sh=%xs_sh
%x_frtp 22:4 !function=times_2
@@ -512,6 +512,12 @@ SRAW 011111 ..... ..... ..... 1100011000 .
@X_rc
SRAWI 011111 ..... ..... ..... 1100111000 . @X_rc
SRW 011111 ..... ..... ..... 1000011000 . @X_rc
+SLD 011111 ..... ..... ..... 0000011011 . @X_rc
+SRD 011111 ..... ..... ..... 1000011011 . @X_rc
+SRAD 011111 ..... ..... ..... 1100011010 . @X_rc
+SRADI 011111 ..... ..... ..... 110011101 . . @XS
+
+EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS
## BCD Assist
@@ -1372,9 +1378,6 @@ DST 011111 ..... ..... ..... 0101010110 - @X
DSTST 011111 ..... ..... ..... 0101110110 - @X
DSS 011111 ..... ..... ..... 1100110110 - @X
-##Extend Sign Word and Shift Left Immediate XS-form
-EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS
-
## Load and Reserve Instructions
LBARX 011111 ..... ..... ..... 0000110100 . @X_rc
LHARX 011111 ..... ..... ..... 0001110100 . @X_rc
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b161f930ec..8e8076a92c 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -261,7 +261,7 @@ target_ulong helper_SRAW(CPUPPCState *env, target_ulong
value,
}
#if defined(TARGET_PPC64)
-target_ulong helper_srad(CPUPPCState *env, target_ulong value,
+target_ulong helper_SRAD(CPUPPCState *env, target_ulong value,
target_ulong shift)
{
int64_t ret;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5be508fcb1..1fc2cd0b14 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2313,95 +2313,6 @@ static void gen_rldimi(DisasContext *ctx, int mbn, int
shn)
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
#endif
-/*** Integer shift ***/
-
-
-#if defined(TARGET_PPC64)
-/* sld & sld. */
-static void gen_sld(DisasContext *ctx)
-{
- TCGv t0, t1;
-
- t0 = tcg_temp_new();
- /* AND rS with a mask that is 0 when rB >= 0x40 */
- tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
- tcg_gen_sari_tl(t0, t0, 0x3f);
- tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
- t1 = tcg_temp_new();
- tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
- tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
- if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
- }
-}
-
-/* srad & srad. */
-static void gen_srad(DisasContext *ctx)
-{
- gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env,
- cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
- if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
- }
-}
-/* sradi & sradi. */
-static inline void gen_sradi(DisasContext *ctx, int n)
-{
- int sh = SH(ctx->opcode) + (n << 5);
- TCGv dst = cpu_gpr[rA(ctx->opcode)];
- TCGv src = cpu_gpr[rS(ctx->opcode)];
- if (sh == 0) {
- tcg_gen_mov_tl(dst, src);
- tcg_gen_movi_tl(cpu_ca, 0);
- if (is_isa300(ctx)) {
- tcg_gen_movi_tl(cpu_ca32, 0);
- }
- } else {
- TCGv t0;
- tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
- t0 = tcg_temp_new();
- tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
- tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
- tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
- if (is_isa300(ctx)) {
- tcg_gen_mov_tl(cpu_ca32, cpu_ca);
- }
- tcg_gen_sari_tl(dst, src, sh);
- }
- if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_Rc0(ctx, dst);
- }
-}
-
-static void gen_sradi0(DisasContext *ctx)
-{
- gen_sradi(ctx, 0);
-}
-
-static void gen_sradi1(DisasContext *ctx)
-{
- gen_sradi(ctx, 1);
-}
-
-/* srd & srd. */
-static void gen_srd(DisasContext *ctx)
-{
- TCGv t0, t1;
-
- t0 = tcg_temp_new();
- /* AND rS with a mask that is 0 when rB >= 0x40 */
- tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
- tcg_gen_sari_tl(t0, t0, 0x3f);
- tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
- t1 = tcg_temp_new();
- tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
- tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
- if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
- }
-}
-#endif
-
/*** Addressing modes ***/
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
@@ -5708,13 +5619,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000,
PPC_NONE, PPC2_ISA300),
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-#if defined(TARGET_PPC64)
-GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
-GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
-GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
-GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
-GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
-#endif
/* handles lfdp, lxsd, lxssp */
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
/* handles stfdp, stxsd, stxssp */
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 234404e459..9f669894a3 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -486,6 +486,76 @@ static bool do_add_const_XO(DisasContext *ctx, arg_XO_ta
*a, TCGv const_val,
return true;
}
+static bool do_shift_X_rc(DisasContext *ctx, arg_X_rc *a,
+ void(*op)(TCGv, TCGv, TCGv))
+{
+ REQUIRE_64BIT(ctx);
+#if defined(TARGET_PPC64)
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ /* AND rt with a mask that is 0 when rb >= 0x40 */
+ tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x39);
+ tcg_gen_sari_tl(t0, t0, 0x3f);
+ tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0);
+ tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x3f);
+ op(cpu_gpr[a->ra], t0, t1);
+ if (unlikely(a->rc)) {
+ gen_set_Rc0(ctx, cpu_gpr[a->ra]);
+ }
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_SRAD(DisasContext *ctx, arg_SRAD *a)
+{
+ REQUIRE_64BIT(ctx);
+#if defined(TARGET_PPC64)
+ gen_helper_SRAD(cpu_gpr[a->ra], tcg_env, cpu_gpr[a->rt], cpu_gpr[a->rb]);
+ if (unlikely(a->rc)) {
+ gen_set_Rc0(ctx, cpu_gpr[a->ra]);
+ }
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_SRADI(DisasContext *ctx, arg_SRADI *a)
+{
+ REQUIRE_64BIT(ctx);
+#if defined(TARGET_PPC64)
+ int sh = a->sh;
+ TCGv dst = cpu_gpr[a->ra];
+ TCGv src = cpu_gpr[a->rs];
+ if (sh == 0) {
+ tcg_gen_mov_tl(dst, src);
+ tcg_gen_movi_tl(cpu_ca, 0);
+ if (is_isa300(ctx)) {
+ tcg_gen_movi_tl(cpu_ca32, 0);
+ }
+ } else {
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
+ tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
+ tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
+ tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+ }
+ tcg_gen_sari_tl(dst, src, sh);
+ }
+ if (unlikely(a->rc)) {
+ gen_set_Rc0(ctx, dst);
+ }
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
TRANS(ADD, do_add_XO, false, false);
TRANS(ADDC, do_add_XO, false, true);
TRANS(ADDE, do_add_XO, true, true);
@@ -493,6 +563,8 @@ TRANS(ADDME, do_add_const_XO, tcg_constant_tl(-1LL), true,
true);
TRANS(ADDZE, do_add_const_XO, tcg_constant_tl(0), true, true);
TRANS(ADDIC, do_add_D, false, true, false, false);
TRANS(ADDIC_, do_add_D, false, true, false, true);
+TRANS(SLD, do_shift_X_rc, tcg_gen_shl_tl);
+TRANS(SRD, do_shift_X_rc, tcg_gen_shr_tl);
static bool trans_SUBFIC(DisasContext *ctx, arg_D *a)
{
--
2.53.0
