From: Shivang Upadhyay <[email protected]>
Move below instructions to decodetree specification :
mfcr, mfocr,
mtcrf, mtocrf : XFX-form
The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' flag.
Signed-off-by: Shivang Upadhyay <[email protected]>
Signed-off-by: Chinmay Rath <[email protected]>
---
target/ppc/insn32.decode | 8 +++
target/ppc/translate.c | 62 -----------------
target/ppc/translate/fixedpoint-impl.c.inc | 79 ++++++++++++++++++++++
3 files changed, 87 insertions(+), 62 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a4454a2292..928ae1f48b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -70,6 +70,9 @@
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+&XFX rt fxm
+@XFX ...... rt:5 . fxm:8 ...... ..... . &XFX
+
%md_sh 1:1 11:5
%md_mb 5:1 6:5
&MD rs ra sh mb rc
@@ -648,6 +651,11 @@ FSEL 111111 ..... ..... ..... ..... 10111 . @A
### Move To/From System Register Instructions
+MFCR 011111 ..... 0.... ....- 0000010011 - @XFX
+MFOCR 011111 ..... 1.... ....- 0000010011 - @XFX
+MTCRF 011111 ..... 0.... ....- 0010010000 - @XFX
+MTOCRF 011111 ..... 1.... ....- 0010010000 - @XFX
+
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d1e9ab61e9..d5369549ee 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3131,40 +3131,6 @@ static void gen_mcrxrx(DisasContext *ctx)
}
#endif
-/* mfcr mfocrf */
-static void gen_mfcr(DisasContext *ctx)
-{
- uint32_t crm, crn;
-
- if (likely(ctx->opcode & 0x00100000)) {
- crm = CRM(ctx->opcode);
- if (likely(crm && ((crm & (crm - 1)) == 0))) {
- crn = ctz32(crm);
- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
- tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rD(ctx->opcode)], crn * 4);
- }
- } else {
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_mov_i32(t0, cpu_crf[0]);
- tcg_gen_shli_i32(t0, t0, 4);
- tcg_gen_or_i32(t0, t0, cpu_crf[1]);
- tcg_gen_shli_i32(t0, t0, 4);
- tcg_gen_or_i32(t0, t0, cpu_crf[2]);
- tcg_gen_shli_i32(t0, t0, 4);
- tcg_gen_or_i32(t0, t0, cpu_crf[3]);
- tcg_gen_shli_i32(t0, t0, 4);
- tcg_gen_or_i32(t0, t0, cpu_crf[4]);
- tcg_gen_shli_i32(t0, t0, 4);
- tcg_gen_or_i32(t0, t0, cpu_crf[5]);
- tcg_gen_shli_i32(t0, t0, 4);
- tcg_gen_or_i32(t0, t0, cpu_crf[6]);
- tcg_gen_shli_i32(t0, t0, 4);
- tcg_gen_or_i32(t0, t0, cpu_crf[7]);
- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
- }
-}
-
/* mfmsr */
static void gen_mfmsr(DisasContext *ctx)
{
@@ -3245,32 +3211,6 @@ static void gen_mftb(DisasContext *ctx)
gen_op_mfspr(ctx);
}
-/* mtcrf mtocrf*/
-static void gen_mtcrf(DisasContext *ctx)
-{
- uint32_t crm, crn;
-
- crm = CRM(ctx->opcode);
- if (likely((ctx->opcode & 0x00100000))) {
- if (crm && ((crm & (crm - 1)) == 0)) {
- TCGv_i32 temp = tcg_temp_new_i32();
- crn = ctz32(crm);
- tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_shri_i32(temp, temp, crn * 4);
- tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
- }
- } else {
- TCGv_i32 temp = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
- for (crn = 0 ; crn < 8 ; crn++) {
- if (crm & (1 << crn)) {
- tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
- tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
- }
- }
- }
-}
-
/* mtmsr */
#if defined(TARGET_PPC64)
static void gen_mtmsrd(DisasContext *ctx)
@@ -5067,11 +5007,9 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001,
PPC_64H),
GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
-GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
-GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
#if defined(TARGET_PPC64)
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 4d35133adc..d768a0454d 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -461,6 +461,85 @@ static bool trans_ADDEX(DisasContext *ctx, arg_X *a)
return true;
}
+static bool trans_MTCRF(DisasContext *ctx, arg_MTCRF *a)
+{
+ uint32_t crm, crn;
+
+ crm = a->fxm;
+
+ TCGv_i32 temp = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]);
+
+ for (crn = 0 ; crn < 8 ; crn++) {
+ if (crm & (1 << crn)) {
+ tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
+ tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
+ }
+ }
+
+ return true;
+}
+
+static bool trans_MTOCRF(DisasContext *ctx, arg_MTOCRF *a)
+{
+
+ uint32_t crm, crn;
+
+ crm = a->fxm;
+
+ /* Checking crm > 0 and set_bits(crm) == 1 */
+ if (crm && ((crm & (crm - 1)) == 0)) {
+ TCGv_i32 temp = tcg_temp_new_i32();
+ crn = ctz32(crm);
+ tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]);
+ tcg_gen_shri_i32(temp, temp, crn * 4);
+ tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
+ }
+
+ return true;
+}
+
+static bool trans_MFOCR(DisasContext *ctx, arg_MFOCR *a)
+{
+ uint32_t crm, crn;
+
+ crm = a->fxm;
+
+ /* Checking crm > 0 and set_bits(crm) == 1 */
+ if (likely(crm && ((crm & (crm - 1)) == 0))) {
+ crn = ctz32(crm);
+ tcg_gen_extu_i32_tl(cpu_gpr[a->rt], cpu_crf[7 - crn]);
+ tcg_gen_shli_tl(cpu_gpr[a->rt],
+ cpu_gpr[a->rt], crn * 4);
+ }
+
+ return true;
+}
+
+static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a)
+{
+
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_mov_i32(t0, cpu_crf[0]);
+ tcg_gen_shli_i32(t0, t0, 4);
+ tcg_gen_or_i32(t0, t0, cpu_crf[1]);
+ tcg_gen_shli_i32(t0, t0, 4);
+ tcg_gen_or_i32(t0, t0, cpu_crf[2]);
+ tcg_gen_shli_i32(t0, t0, 4);
+ tcg_gen_or_i32(t0, t0, cpu_crf[3]);
+ tcg_gen_shli_i32(t0, t0, 4);
+ tcg_gen_or_i32(t0, t0, cpu_crf[4]);
+ tcg_gen_shli_i32(t0, t0, 4);
+ tcg_gen_or_i32(t0, t0, cpu_crf[5]);
+ tcg_gen_shli_i32(t0, t0, 4);
+ tcg_gen_or_i32(t0, t0, cpu_crf[6]);
+ tcg_gen_shli_i32(t0, t0, 4);
+ tcg_gen_or_i32(t0, t0, cpu_crf[7]);
+ tcg_gen_extu_i32_tl(cpu_gpr[a->rt], t0);
+
+ return true;
+}
+
static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca,
bool compute_ov, bool compute_rc0)
{
--
2.53.0
