On 5/19/26 09:22, James Hilliard wrote:
+CP2_MF_I64(CVM_MF_GFM_MUL_REFLECT0, gfm_reflect_mul[0]);
+CP2_MF_I64(CVM_MF_GFM_MUL_REFLECT1, gfm_reflect_mul[1]);
These perform rt = reflect(GFMMUL[i]), not read from separate storage.
+CP2_MF_I64(CVM_MF_GFM_RESINP_REFLECT0, gfm_reflect_resinp[0]);
+CP2_MF_I64(CVM_MF_GFM_RESINP_REFLECT1, gfm_reflect_resinp[1]);
Likewise.
+CP2_MF_I64(CVM_MF_3DES_RESULT_MT, des3_result);
Correct implementation, but it's named CVM_MF_KAS_RESULT.
+CP2_MF_HELPER(CVM_MF_HSH_DATW0, hsh_datw0);
+CP2_MF_HELPER(CVM_MF_HSH_DATW1, hsh_datw1);
+CP2_MF_HELPER(CVM_MF_HSH_DATW2, hsh_datw2);
+CP2_MF_HELPER(CVM_MF_HSH_DATW3, hsh_datw3);
+CP2_MF_HELPER(CVM_MF_HSH_DATW4, hsh_datw4);
+CP2_MF_HELPER(CVM_MF_HSH_DATW5, hsh_datw5);
+CP2_MF_HELPER(CVM_MF_HSH_DATW6, hsh_datw6);
+CP2_MF_HELPER(CVM_MF_HSH_DATW7, hsh_datw7);
+CP2_MF_HELPER(CVM_MF_HSH_DATW8, hsh_datw8);
+CP2_MF_HELPER(CVM_MF_HSH_DATW9, hsh_datw9);
+CP2_MF_HELPER(CVM_MF_HSH_DATW10, hsh_datw10);
+CP2_MF_HELPER(CVM_MF_HSH_DATW11, hsh_datw11);
+CP2_MF_HELPER(CVM_MF_HSH_DATW12, hsh_datw12);
+CP2_MF_HELPER(CVM_MF_HSH_DATW13, hsh_datw13);
+CP2_MF_HELPER(CVM_MF_HSH_DATW14, hsh_datw14);
+CP2_MF_HELPER(CVM_MF_HSH_DATW15, hsh_datw15);
These should be straight 64-bit loads from HASHDAT[i].
CVM_MF_HSH_DATi should use something like
static bool trans_octeon_cp_mf_hsh_dat(DisasContext *ctx, arg_cp2 *a, int i)
{
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_ld_i64(t0, tcg_env, OCTEON_CRYPTO_OFFSET(hash_dat[2 * i + 0]));
tcg_gen_ld_i64(t1, tcg_env, OCTEON_CRYPTO_OFFSET(hash_dat[2 * i + 1]));
tcg_gen_concat32_i64(t0, t0, t1);
gen_store_gpr(t0, a->rt);
return true;
}
+CP2_MT_I64(CVM_MT_HSH_DAT0, hsh_dat[0]);
+CP2_MT_I64(CVM_MT_HSH_DAT1, hsh_dat[1]);
+CP2_MT_I64(CVM_MT_HSH_DAT2, hsh_dat[2]);
+CP2_MT_I64(CVM_MT_HSH_DAT3, hsh_dat[3]);
+CP2_MT_I64(CVM_MT_HSH_DAT4, hsh_dat[4]);
+CP2_MT_I64(CVM_MT_HSH_DAT5, hsh_dat[5]);
+CP2_MT_I64(CVM_MT_HSH_DAT6, hsh_dat[6]);
Similarly
static bool trans_octeon_cp_mt_hsh_dat(DisasContext *ctx, arg_cp2 *a, int i)
{
TCGv_i64 t = tcg_temp_new_i64();
gen_load_gpr(t, a->rt);
tcg_gen_st32_i64(t, tcg_env, OCTEON_CRYPTO_OFFSET(hash_dat[2 * i + 1])
+ (HOST_WORDS_BIG_ENDIAN ? 4 : 0));
tcg_gen_shri_i64(t, t, 32);
tcg_gen_st32_i64(t, tcg_env, OCTEON_CRYPTO_OFFSET(hash_dat[2 * i + 0])
+ (HOST_WORDS_BIG_ENDIAN ? 4 : 0));
return true;
}
+CP2_MT_I64(CVM_MT_GFM_MUL_REFLECT0, gfm_reflect_mul[0]);
+CP2_MT_I64(CVM_MT_GFM_MUL_REFLECT1, gfm_reflect_mul[1]);
These perform GFMMUL[i] = reflect(rt).
+CP2_MT_I64(CVM_MT_GFM_XOR0_REFLECT, gfm_reflect_xor0);
This performs GFMRESINP[0] ^= reflect(rt).
+CP2_MT_U8(CVM_MT_AES_KEYLENGTH, aes_keylen);
AESKEYLEN is 2 bits. You need to mask this write.
+CP2_MT_U32(CVM_MT_CRC_WRITE_LEN, crc_len);
CRCLEN is 4 bits. You need to mask this write.
+CP2_MT_U32(CVM_MT_CRC_WRITE_POLYNOMIAL, crc_poly);
The correct name appears to be CVM_MT_CRC_POLYNOMIAL
+CP2_MT_U32(CVM_MT_CRC_WRITE_POLYNOMIAL_REFLECT, crc_poly);
CVM_MT_CRC_POLYNOMIAL_REFLECT, and is missing the reflect.
CRCPOLY<31:0> = byte_bit_reflect(rt<31:0>)
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_IV_REFLECT, crc_write_iv_reflect);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_BYTE, crc_write_byte);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_HALF, crc_write_half);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_WORD, crc_write_word);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_BYTE_REFLECT, crc_write_byte_reflect);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_HALF_REFLECT, crc_write_half_reflect);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_WORD_REFLECT, crc_write_word_reflect);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_DWORD, crc_write_dword);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_VAR, crc_write_var);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_DWORD_REFLECT, crc_write_dword_reflect);
+CP2_MT_HELPER(CVM_MT_CRC_WRITE_VAR_REFLECT, crc_write_var_reflect);
Misnamed? s/_WRITE//.
+CP2_MT_HELPER(CVM_MT_SHA3_DAT24, sha3_dat24);
+CP2_MT_HELPER(CVM_MT_SHA3_DAT15, sha3_dat15);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT0, sha3_xordat0);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT1, sha3_xordat1);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT2, sha3_xordat2);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT3, sha3_xordat3);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT4, sha3_xordat4);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT5, sha3_xordat5);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT6, sha3_xordat6);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT7, sha3_xordat7);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT8, sha3_xordat8);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT9, sha3_xordat9);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT10, sha3_xordat10);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT11, sha3_xordat11);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT12, sha3_xordat12);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT13, sha3_xordat13);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT14, sha3_xordat14);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT15, sha3_xordat15);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT16, sha3_xordat16);
+CP2_MT_HELPER(CVM_MT_SHA3_XORDAT17, sha3_xordat17);
+CP2_MT_HELPER(CVM_MT_SHA3_STARTOP, sha3_startop);
FWIW, SHA3 is missing from the document you shared.
+CP2_MT_HELPER(CVM_MT_HSH_STARTSHA_COMPAT, hsh_startsha_compat);
What's this? I don't see anything for 0x0057 in either the cn50xx or cn71xx
docs.
+CP2_MT_HELPER(CVM_MT_HSH_DATW0, hsh_datw0);
+CP2_MT_HELPER(CVM_MT_HSH_DATW1, hsh_datw1);
+CP2_MT_HELPER(CVM_MT_HSH_DATW2, hsh_datw2);
+CP2_MT_HELPER(CVM_MT_HSH_DATW3, hsh_datw3);
+CP2_MT_HELPER(CVM_MT_HSH_DATW4, hsh_datw4);
+CP2_MT_HELPER(CVM_MT_HSH_DATW5, hsh_datw5);
+CP2_MT_HELPER(CVM_MT_HSH_DATW6, hsh_datw6);
+CP2_MT_HELPER(CVM_MT_HSH_DATW7, hsh_datw7);
+CP2_MT_HELPER(CVM_MT_HSH_DATW8, hsh_datw8);
+CP2_MT_HELPER(CVM_MT_HSH_DATW9, hsh_datw9);
+CP2_MT_HELPER(CVM_MT_HSH_DATW10, hsh_datw10);
+CP2_MT_HELPER(CVM_MT_HSH_DATW11, hsh_datw11);
+CP2_MT_HELPER(CVM_MT_HSH_DATW12, hsh_datw12);
+CP2_MT_HELPER(CVM_MT_HSH_DATW13, hsh_datw13);
+CP2_MT_HELPER(CVM_MT_HSH_DATW14, hsh_datw14);
+CP2_MT_HELPER(CVM_MT_HSH_DATW15, hsh_datw15);
+CP2_MT_HELPER(CVM_MT_HSH_IVW0, hsh_ivw0);
+CP2_MT_HELPER(CVM_MT_HSH_IVW1, hsh_ivw1);
+CP2_MT_HELPER(CVM_MT_HSH_IVW2, hsh_ivw2);
+CP2_MT_HELPER(CVM_MT_HSH_IVW3, hsh_ivw3);
+CP2_MT_HELPER(CVM_MT_HSH_IVW4, hsh_ivw4);
+CP2_MT_HELPER(CVM_MT_HSH_IVW5, hsh_ivw5);
+CP2_MT_HELPER(CVM_MT_HSH_IVW6, hsh_ivw6);
+CP2_MT_HELPER(CVM_MT_HSH_IVW7, hsh_ivw7);
These should be straight 64-bit stores.
+CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR0, llm_read_addr0);
+CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR0, llm_write_addr0);
+CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR0, llm_read64_addr0);
+CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR0, llm_write64_addr0);
+CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR1, llm_read_addr1);
+CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR1, llm_write_addr1);
+CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR1, llm_read64_addr1);
+CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR1, llm_write64_addr1);
FWIW, Chord and LLM are missing from the document you shared.
r~
