Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/cpu-features.h | 5 +++++
target/arm/tcg/translate-sme.c | 15 +++++++++++++--
target/arm/tcg/sme.decode | 6 ++++++
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 1fde3e9231..f9c979d20b 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -1622,6 +1622,11 @@ static inline bool isar_feature_aa64_sme2_faminmax(const
ARMISARegisters *id)
return isar_feature_aa64_sme2(id) && isar_feature_aa64_faminmax(id);
}
+static inline bool isar_feature_aa64_sme2_f8cvt(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_sme2(id) && isar_feature_aa64_f8cvt(id);
+}
+
static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
{
return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id);
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index a67501226f..e2d17de165 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -707,9 +707,12 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a,
{
int esz = a->esz, n, dn, vsz, mofs;
bool overlap = false;
- gen_helper_gvec_3_ptr *fn;
+ gen_helper_gvec_3_ptr *fn = fns[esz];
TCGv_ptr fpst;
+ if (fn == NULL) {
+ return false;
+ }
/* These insns use MO_8 to encode BFloat16. */
if (esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {
return false;
@@ -719,7 +722,6 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a,
}
fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);
- fn = fns[esz];
n = a->n;
dn = a->zdn;
mofs = vec_full_reg_offset(s, a->zm);
@@ -831,6 +833,15 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[4] = {
};
TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famin)
+static gen_helper_gvec_3_ptr * const f_vector_fscale[4] = {
+ NULL,
+ gen_helper_gvec_fscale_h,
+ gen_helper_gvec_fscale_s,
+ gen_helper_gvec_fscale_d,
+};
+TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_z2z_n1_fpst, a, f_vector_fscale)
+TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_z2z_nn_fpst, a, f_vector_fscale)
+
/* Add/Sub vector Z[m] to each Z[n*N] with result in ZA[d*N]. */
static bool do_azz_n1(DisasContext *s, arg_azz_n *a, int esz,
GVecGen3FnVar *fn)
diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode
index 9dec7318a4..ee874be1a6 100644
--- a/target/arm/tcg/sme.decode
+++ b/target/arm/tcg/sme.decode
@@ -250,6 +250,9 @@ ADD_n1 1100000 1 .. 10 .... 1010.0 11000 .... 0
@z2z_4x1
SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_2x1
SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_4x1
+FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1
+FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1
+
### SME2 Multi-vector Multiple Vectors SVE Destructive
%zm_ax2 17:4 !function=times_2
@@ -291,6 +294,9 @@ FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0
@z2z_4x4
FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2
FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4
+FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2
+FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4
+
### SME2 Multi-vector Multiple and Single Array Vectors
&azz_n n off rv zn zm
--
2.43.0
