The existing pattern is BFCVT (single-precision to BFloat16). In preparation for introducing more insns of the same name, append the operand sizes.
Signed-off-by: Richard Henderson <[email protected]> --- target/arm/tcg/helper-sme-defs.h | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/translate-sme.c | 4 ++-- target/arm/tcg/sme.decode | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/helper-sme-defs.h b/target/arm/tcg/helper-sme-defs.h index c551797c6f..01aad4c231 100644 --- a/target/arm/tcg/helper-sme-defs.h +++ b/target/arm/tcg/helper-sme-defs.h @@ -250,7 +250,7 @@ DEF_HELPER_FLAGS_5(sme2_umlsll_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, DEF_HELPER_FLAGS_5(sme2_usmlall_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme2_sumlall_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sme2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(sme2_bfcvt_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_4(sme2_bfcvtn, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_4(sme2_fcvt_n, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_4(sme2_fcvtn, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 0055e97a2b..a0f03c4671 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1742,7 +1742,7 @@ DO_MLALL_IDX(sme2_sumlall_idx_s, uint32_t, int8_t, uint8_t, H4, H1, +) #undef DO_MLALL_IDX /* Convert and compress */ -void HELPER(sme2_bfcvt)(void *vd, void *vs, float_status *fpst, uint32_t desc) +void HELPER(sme2_bfcvt_hs)(void *vd, void *vs, float_status *fpst, uint32_t desc) { ARMVectorReg scratch; size_t oprsz = simd_oprsz(desc); diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index e2d17de165..88c1d78c40 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1448,8 +1448,8 @@ static bool do_zz_fpst(DisasContext *s, arg_zz_n *a, int data, return true; } -TRANS_FEAT(BFCVT, aa64_sme2, do_zz_fpst, a, 0, - FPST_A64, gen_helper_sme2_bfcvt) +TRANS_FEAT(BFCVT_hs, aa64_sme2, do_zz_fpst, a, 0, + FPST_A64, gen_helper_sme2_bfcvt_hs) TRANS_FEAT(BFCVTN, aa64_sme2, do_zz_fpst, a, 0, FPST_A64, gen_helper_sme2_bfcvtn) TRANS_FEAT(FCVT_n, aa64_sme2, do_zz_fpst, a, 0, diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index ee874be1a6..7a8e1abb59 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -789,7 +789,7 @@ SUB_aaz_d 11000001 111 000010 .. 111 ...00 11 ... @az_4x4_o3 @zz_4x2_n1 ........ ... ..... ...... .... . ..... \ &zz_n n=1 zd=%zd_ax4 zn=%zn_ax2 -BFCVT 11000001 011 00000 111000 ....0 ..... @zz_1x2 +BFCVT_hs 11000001 011 00000 111000 ....0 ..... @zz_1x2 BFCVTN 11000001 011 00000 111000 ....1 ..... @zz_1x2 FCVT_n 11000001 001 00000 111000 ....0 ..... @zz_1x2 -- 2.43.0
