On Wed, May 20, 2026 at 03:13:05PM +0800, Anton Johansson via wrote: > Macros are removed and replaced with inlined ternary statements. The > now empty sifive_cpu.h header is then removed. > > Reviewed-by: Philippe Mathieu-Daudé <[email protected]> > Reviewed-by: Pierrick Bouvier <[email protected]> > Signed-off-by: Anton Johansson <[email protected]> Reviewed-by: Chao Liu <[email protected]>
> --- > include/hw/riscv/sifive_cpu.h | 31 ------------------------------- > include/hw/riscv/sifive_e.h | 1 - > include/hw/riscv/sifive_u.h | 1 - > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 7 +++++-- > 5 files changed, 7 insertions(+), 36 deletions(-) > > diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h > deleted file mode 100644 > index 136799633a..0000000000 > --- a/include/hw/riscv/sifive_cpu.h > +++ /dev/null > @@ -1,31 +0,0 @@ > -/* > - * SiFive CPU types > - * > - * Copyright (c) 2017 SiFive, Inc. > - * Copyright (c) 2019 Bin Meng <[email protected]> > - * > - * This program is free software; you can redistribute it and/or modify it > - * under the terms and conditions of the GNU General Public License, > - * version 2 or later, as published by the Free Software Foundation. > - * > - * This program is distributed in the hope it will be useful, but WITHOUT > - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > - * more details. > - * > - * You should have received a copy of the GNU General Public License along > with > - * this program. If not, see <http://www.gnu.org/licenses/>. > - */ > - > -#ifndef HW_SIFIVE_CPU_H > -#define HW_SIFIVE_CPU_H > - > -#if defined(TARGET_RISCV32) > -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 > -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 > -#elif defined(TARGET_RISCV64) > -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 > -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 > -#endif > - > -#endif /* HW_SIFIVE_CPU_H */ > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h > index 4cf902ebc0..0f0d407d5d 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -20,7 +20,6 @@ > #define HW_SIFIVE_E_H > > #include "hw/riscv/riscv_hart.h" > -#include "hw/riscv/sifive_cpu.h" > #include "hw/gpio/sifive_gpio.h" > #include "hw/misc/sifive_e_aon.h" > #include "hw/core/boards.h" > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index e4c9860d50..bfaaf254af 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -24,7 +24,6 @@ > #include "hw/dma/sifive_pdma.h" > #include "hw/net/cadence_gem.h" > #include "hw/riscv/riscv_hart.h" > -#include "hw/riscv/sifive_cpu.h" > #include "hw/gpio/sifive_gpio.h" > #include "hw/misc/sifive_u_otp.h" > #include "hw/misc/sifive_u_prci.h" > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 71925583bd..76505fdc4d 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -151,7 +151,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc, > const void *data) > mc->desc = "RISC-V Board compatible with SiFive E SDK"; > mc->init = sifive_e_machine_init; > mc->max_cpus = 1; > - mc->default_cpu_type = SIFIVE_E_CPU; > + mc->default_cpu_type = (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_E51 > + : TYPE_RISCV_CPU_SIFIVE_E31; > mc->default_ram_id = "riscv.sifive.e.ram"; > mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 6a637e3b86..b1f5bad8aa 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -723,7 +723,8 @@ static void sifive_u_machine_class_init(ObjectClass *oc, > const void *data) > mc->init = sifive_u_machine_init; > mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + > SIFIVE_U_COMPUTE_CPU_COUNT; > mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; > - mc->default_cpu_type = SIFIVE_U_CPU; > + mc->default_cpu_type = (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_U54 > + : TYPE_RISCV_CPU_SIFIVE_U34; > mc->default_cpus = mc->min_cpus; > mc->default_ram_id = "riscv.sifive.u.ram"; > mc->auto_create_sdcard = true; > @@ -756,6 +757,8 @@ type_init(sifive_u_machine_init_register_types) > static void sifive_u_soc_instance_init(Object *obj) > { > SiFiveUSoCState *s = RISCV_U_SOC(obj); > + const char *e_cpu_type = (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_E51 > + : TYPE_RISCV_CPU_SIFIVE_E31; > > object_initialize_child(obj, "e-cluster", &s->e_cluster, > TYPE_CPU_CLUSTER); > qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); > @@ -764,7 +767,7 @@ static void sifive_u_soc_instance_init(Object *obj) > TYPE_RISCV_HART_ARRAY); > qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); > qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); > - qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); > + qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", e_cpu_type); > qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); > > object_initialize_child(obj, "u-cluster", &s->u_cluster, > TYPE_CPU_CLUSTER); > > -- > 2.52.0 > >
