On Wed, 20 May 2026 at 19:23, Richard Henderson <[email protected]> wrote: > > Signed-off-by: Richard Henderson <[email protected]> > --- > target/arm/tcg/translate-a64.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c > index b013dd51cb..d2a4b0fadc 100644 > --- a/target/arm/tcg/translate-a64.c > +++ b/target/arm/tcg/translate-a64.c > @@ -2899,6 +2899,10 @@ static void handle_sys(DisasContext *s, bool isread, > } > > if (!skip_fp_access_checks) { > + if ((ri->type & ARM_CP_FPMR) && s->fpmr_el != 0) { > + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, s->fpmr_el); > + return; > + } > if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { > return; > } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
It took me a little while to work out how we do the traps on CPACR_EL1.FPEN etc, but we mark the register as both ARM_CP_FPMR and ARM_CP_FPU, and the latter handles the fp access trap part. Hopefully nobody in future "simplifies" this if() into the if...else if...else if ladder of ARM_CP_FPU/SVE/SME type checks :-) Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
