Richard Henderson <[email protected]> writes:
> Signed-off-by: Richard Henderson <[email protected]>
> ---
> target/arm/cpu-features.h | 9 +++++++++
> target/arm/helper.c | 8 ++++++--
> target/arm/cpu-sysregs.h.inc | 1 +
> 3 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 4e44245a8b..50776347a5 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -244,6 +244,15 @@ FIELD(ID_AA64ISAR2, CSSC, 52, 4)
> FIELD(ID_AA64ISAR2, LUT, 56, 4)
> FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
>
> +FIELD(ID_AA64ISAR3, CPA, 0, 4)
> +FIELD(ID_AA64ISAR3, FAMINMAX, 4, 4)
> +FIELD(ID_AA64ISAR3, TLBIW, 8, 4)
> +FIELD(ID_AA64ISAR3, PACM, 12, 4)
> +FIELD(ID_AA64ISAR3, LSFE, 16, 4)
> +FIELD(ID_AA64ISAR3, OCCMO, 20, 4)
> +FIELD(ID_AA64ISAR3, LSUI, 24, 4)
> +FIELD(ID_AA64ISAR3, FPRCVT, 28, 4)
> +
> FIELD(ID_AA64PFR0, EL0, 0, 4)
> FIELD(ID_AA64PFR0, EL1, 4, 4)
> FIELD(ID_AA64PFR0, EL2, 8, 4)
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 8240f1b384..6ad01b345f 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6519,11 +6519,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_tid3,
> .resetvalue = GET_IDREG(isar, ID_AA64ISAR2)},
> - { .name = "ID_AA64ISAR3_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> + { .name = "ID_AA64ISAR3_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_tid3,
> - .resetvalue = 0 },
> + .resetvalue = GET_IDREG(isar, ID_AA64ISAR3) },
> { .name = "ID_AA64ISAR4_EL1_RESERVED", .state =
> ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
> .access = PL1_R, .type = ARM_CP_CONST,
> @@ -6752,6 +6752,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> R_ID_AA64ISAR2_BC_MASK |
> R_ID_AA64ISAR2_RPRFM_MASK |
> R_ID_AA64ISAR2_CSSC_MASK },
> + { .name = "ID_AA64ISAR3_EL1",
> + .exported_bits = R_ID_AA64ISAR3_FAMINMAX_MASK |
> + R_ID_AA64ISAR3_LSFE_MASK |
> + R_ID_AA64ISAR3_FPRCVT_MASK },
With this definition should we also add it to arm_clear_aarch64_idregs()
which clears the other ISARs with aarch64=off?
> { .name = "ID_AA64ISAR*_EL1_RESERVED",
> .is_glob = true },
> };
> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
> index 3d1ed40f04..b99579f773 100644
> --- a/target/arm/cpu-sysregs.h.inc
> +++ b/target/arm/cpu-sysregs.h.inc
> @@ -10,6 +10,7 @@ DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)
> DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
> DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
> DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
> +DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3)
> DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
> DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
> DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
