Peter Maydell <[email protected]> writes: > The SVE FCVTLT_hs operation produces a halfprec result, so we should > use the FPST_A64_F16 fpstatus for it.
Maybe I'm reading the Arm ARM wrong (I can't find FCVTLT_hs but I can see FCVTLT in the SVE encodings). But these are all widening operations so I can see halfprec to single, not the other way around. > Getting this wrong means we > will incorrectly set FPCR.IDC for input-denormals when FPCR.AH=1. > > We missed this instruction when we updated the halfproc-to-other > conversion insns to use FPST_A64_F16 in commit e07b48995aaa > as part of implementing FEAT_AHP. > > Cc: [email protected] > Fixes: e07b48995aaa ("target/arm: Use FPST_A64_F16 for halfprec-to-other > conversions")a > Signed-off-by: Peter Maydell <[email protected]> > --- > target/arm/tcg/translate-sve.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c > index bf9f0ae179..59b8c494a8 100644 > --- a/target/arm/tcg/translate-sve.c > +++ b/target/arm/tcg/translate-sve.c > @@ -7827,7 +7827,7 @@ TRANS_FEAT(BFCVTNT, aa64_sme_sve_bf16, > gen_gvec_fpst_arg_zpz, > s->fpcr_ah ? FPST_AH : FPST_A64) > > TRANS_FEAT(FCVTLT_hs, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, > - gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64) > + gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64_F16) > TRANS_FEAT(FCVTLT_sd, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, > gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64) -- Alex Bennée Virtualisation Tech Lead @ Linaro
