On Wed, May 20, 2026 at 3:28 AM Philippe Mathieu-Daudé <[email protected]> wrote: > > Host user-emulation headers were renamed in commits ba0e7333620 > ("configure: Merge riscv32 and riscv64 host architectures") and > bbf15aaf7c7 ("common-user: Move safe-syscall.* from linux-user"), > then covered in commit 355cdac7d86 ("MAINTAINERS: Add > common-user/host/riscv to RISC-V section"). Remove the obsolete > entries. > > test_riscv64_sifive_u.py was renamed in commit e1a8572a8d7 > ("tests/functional: Move riscv32/riscv64 tests into target-specific > folders"). > > Reported-by: Pierrick Bouvier <[email protected]> > Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > MAINTAINERS | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 73b7ebf1d7e..0a1cc0e51a2 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -361,8 +361,6 @@ F: hw/riscv/ > F: hw/intc/riscv* > F: include/hw/char/riscv_htif.h > F: include/hw/riscv/ > -F: linux-user/host/riscv32/ > -F: linux-user/host/riscv64/ > F: common-user/host/riscv* > F: tests/functional/riscv32 > F: tests/functional/riscv64 > @@ -1783,7 +1781,7 @@ S: Supported > F: docs/system/riscv/sifive_u.rst > F: hw/*/*sifive*.c > F: include/hw/*/*sifive*.h > -F: tests/functional/test_riscv64_sifive_u.py > +F: tests/functional/riscv64/test_sifive_u.py > > AMD Microblaze-V Generic Board > M: Sai Pavan Boddu <[email protected]> > -- > 2.53.0 > >
