Hi All,
I see there is a test case that fails during the CI run.
https://gitlab.com/rathc/qemu/-/jobs/14481511189/
Looking into it
Thanks,
vishalc
On 20/05/26 21:37, Chinmay Rath wrote:
We recently had a QEMU decodetree hackathon at our org focusing on moving
instructions to decodetree specification. I have consolidated the patches
generated out of this effort in this series. Though I have done a round
of review on all of them, might share some more review comments later.
The checkpatch.pl script emits false error for a couple of patches which
are of the following nature :
TRANS(STWAT, do_st_atomic, DEF_MEMOP(MO_UL))
static bool trans_LDAT(DisasContext *ctx, arg_LDAT *a)
^
I see this happening in the last pointer argument in function
definitions after macros (like TRANS(..) in this case).
Richard, Peter, Stefan,
Could you please advise if it would be okay to have the above false
positive in the patches ?
Gitlab CI: https://gitlab.com/rathc/qemu/-/pipelines/2540725424
Please note that check-python-tox and migration-compat-aarch64 from CI
fails in the upstream master branch as seen in the following:
https://gitlab.com/rathc/qemu/-/pipelines/2537246569
Thanks,
Chinmay
Aboorva Devarajan (3):
target/ppc: Move vector merge instructions to decodetree
target/ppc: Move vector pack instructions to decodetree
target/ppc: Move GPR atomic load/store instructions to decodetree
Amit Machhiwal (2):
target/ppc: Move fixed-point Shift insns to decodetree
target/ppc: Move fixed-point byte-reversal store insns to decodetree
Mukesh Kumar Chaurasiya (IBM) (2):
target/ppc: convert slw,srw instruction via decode spec
target/ppc: convert sraw[i] instruction via decode spec
Nikhil Kumar Singh (3):
target/ppc: Migrate extswsli to decodetree
target/ppc: Migrate atomic loads to decodetree
target/ppc: Convert cache instructions to decodetree
Ojaswin Mujoo (7):
target/ppc: Move isync instruction to decodetree.
target/ppc: Convert b{a, l, la} to decode tree
target/ppc: move various conditional branch insns to decodetree
target/ppc: Fix TRANS* macro variadic arguments handling
target/ppc: Move wait instruction to decodetree
target/ppc: Move sleep & friends to decodetree
target/ppc: Refactor sleep and its variants to use a common helper
Shivang Upadhyay (4):
target/ppc: Move Condition Register access instructions to decodetree.
target/ppc: Move Condition Register logical instructions to
decodetree.
target/ppc: Move Fixed-Point Load/Store String instructions to
decodetree.
target/ppc: Move VMX integer arithmetic and BCD instructions to
decodetree.
Shivani Nittor (1):
target/ppc : Convert mcrf to decode tree
Tanushree Shah (2):
target/ppc: Move rlwimi, rlwinm instructions to decodetree
target/ppc: Move lmw, stmw instructions to decodetree
Utkarsh Verma (1):
target/ppc: Move st{b, h, w, d, q}cx instructions to decodetree
Vishal Chourasia (3):
target/ppc: Move mfmsr, mtmsr[d] instructions to decodetree
target/ppc: Move byte-reverse instructions to decodetree
target/ppc: Move system call and rfi instructions to decodetree
target/ppc/helper.h | 100 +-
target/ppc/insn32.decode | 244 ++
target/ppc/int_helper.c | 76 +-
target/ppc/internal.h | 7 -
target/ppc/mem_helper.c | 18 +-
target/ppc/tcg-excp_helper.c | 10 +-
target/ppc/translate.c | 2592 ++++-------------
target/ppc/translate/branch-impl.c.inc | 181 ++
target/ppc/translate/fixedpoint-impl.c.inc | 936 ++++++
target/ppc/translate/misc-impl.c.inc | 175 ++
.../ppc/translate/processor-ctrl-impl.c.inc | 30 +
target/ppc/translate/storage-ctrl-impl.c.inc | 117 +
target/ppc/translate/vmx-impl.c.inc | 360 +--
target/ppc/translate/vmx-ops.c.inc | 41 -
14 files changed, 2529 insertions(+), 2358 deletions(-)
