From: Shivang Upadhyay <[email protected]>
Move below instructions to decodetree specification :
lsw{i, x},
stsw{i, x} : X-form
The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' flag.
Signed-off-by: Shivang Upadhyay <[email protected]>
Signed-off-by: Chinmay Rath <[email protected]>
---
target/ppc/helper.h | 6 +-
target/ppc/insn32.decode | 7 ++
target/ppc/mem_helper.c | 6 +-
target/ppc/translate.c | 102 --------------------
target/ppc/translate/fixedpoint-impl.c.inc | 103 +++++++++++++++++++++
5 files changed, 116 insertions(+), 108 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index dacc4e223e..50493a72a5 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -45,9 +45,9 @@ DEF_HELPER_1(check_tlb_flush_global, void, env)
DEF_HELPER_3(lmw, void, env, tl, i32)
DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32)
-DEF_HELPER_4(lsw, void, env, tl, i32, i32)
-DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32)
-DEF_HELPER_FLAGS_4(stsw, TCG_CALL_NO_WG, void, env, tl, i32, i32)
+DEF_HELPER_4(LSW, void, env, tl, i32, i32)
+DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32)
+DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32)
DEF_HELPER_FLAGS_3(DCBZ, TCG_CALL_NO_WG, void, env, tl, int)
#ifdef TARGET_PPC64
DEF_HELPER_FLAGS_2(DCBZL, TCG_CALL_NO_WG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index f3a1f7970e..0ec9a4d5de 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -527,6 +527,13 @@ CREQV 010011 ..... ..... ..... 0100100001 - @X
CRANDC 010011 ..... ..... ..... 0010000001 - @X
CRORC 010011 ..... ..... ..... 0110100001 - @X
+# Fixed Point Move Assist Instructions
+
+LSWI 011111 ..... ..... ..... 1 001010101 - @X
+LSWX 011111 ..... ..... ..... 1 000010101 - @X
+STSWI 011111 ..... ..... ..... 1 011010101 - @X
+STSWX 011111 ..... ..... ..... 1 010010101 - @X
+
# Fixed-Point Hash Instructions
HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 5d3d377261..303eec4ee5 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -190,7 +190,7 @@ static void do_lsw(CPUPPCState *env, target_ulong addr,
uint32_t nb,
env->gpr[reg] = val;
}
-void helper_lsw(CPUPPCState *env, target_ulong addr,
+void helper_LSW(CPUPPCState *env, target_ulong addr,
uint32_t nb, uint32_t reg)
{
do_lsw(env, addr, nb, reg, GETPC());
@@ -202,7 +202,7 @@ void helper_lsw(CPUPPCState *env, target_ulong addr,
* this is valid, but rA won't be loaded. For now, I'll follow the
* spec...
*/
-void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
+void helper_LSWX(CPUPPCState *env, target_ulong addr, uint32_t reg,
uint32_t ra, uint32_t rb)
{
if (likely(xer_bc != 0)) {
@@ -218,7 +218,7 @@ void helper_lswx(CPUPPCState *env, target_ulong addr,
uint32_t reg,
}
}
-void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
+void helper_STSW(CPUPPCState *env, target_ulong addr, uint32_t nb,
uint32_t reg)
{
uintptr_t raddr = GETPC();
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 85bdb7deab..fc107399db 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2597,104 +2597,6 @@ static void gen_stmw(DisasContext *ctx)
gen_helper_stmw(tcg_env, t0, t1);
}
-/*** Integer load and store strings ***/
-
-/* lswi */
-/*
- * PowerPC32 specification says we must generate an exception if rA is
- * in the range of registers to be loaded. In an other hand, IBM says
- * this is valid, but rA won't be loaded. For now, I'll follow the
- * spec...
- */
-static void gen_lswi(DisasContext *ctx)
-{
- TCGv t0;
- TCGv_i32 t1, t2;
- int nb = NB(ctx->opcode);
- int start = rD(ctx->opcode);
- int ra = rA(ctx->opcode);
- int nr;
-
- if (ctx->le_mode) {
- gen_align_no_le(ctx);
- return;
- }
- if (nb == 0) {
- nb = 32;
- }
- nr = DIV_ROUND_UP(nb, 4);
- if (unlikely(lsw_reg_in_range(start, nr, ra))) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
- return;
- }
- gen_set_access_type(ctx, ACCESS_INT);
- t0 = tcg_temp_new();
- gen_addr_register(ctx, t0);
- t1 = tcg_constant_i32(nb);
- t2 = tcg_constant_i32(start);
- gen_helper_lsw(tcg_env, t0, t1, t2);
-}
-
-/* lswx */
-static void gen_lswx(DisasContext *ctx)
-{
- TCGv t0;
- TCGv_i32 t1, t2, t3;
-
- if (ctx->le_mode) {
- gen_align_no_le(ctx);
- return;
- }
- gen_set_access_type(ctx, ACCESS_INT);
- t0 = tcg_temp_new();
- gen_addr_reg_index(ctx, t0);
- t1 = tcg_constant_i32(rD(ctx->opcode));
- t2 = tcg_constant_i32(rA(ctx->opcode));
- t3 = tcg_constant_i32(rB(ctx->opcode));
- gen_helper_lswx(tcg_env, t0, t1, t2, t3);
-}
-
-/* stswi */
-static void gen_stswi(DisasContext *ctx)
-{
- TCGv t0;
- TCGv_i32 t1, t2;
- int nb = NB(ctx->opcode);
-
- if (ctx->le_mode) {
- gen_align_no_le(ctx);
- return;
- }
- gen_set_access_type(ctx, ACCESS_INT);
- t0 = tcg_temp_new();
- gen_addr_register(ctx, t0);
- if (nb == 0) {
- nb = 32;
- }
- t1 = tcg_constant_i32(nb);
- t2 = tcg_constant_i32(rS(ctx->opcode));
- gen_helper_stsw(tcg_env, t0, t1, t2);
-}
-
-/* stswx */
-static void gen_stswx(DisasContext *ctx)
-{
- TCGv t0;
- TCGv_i32 t1, t2;
-
- if (ctx->le_mode) {
- gen_align_no_le(ctx);
- return;
- }
- gen_set_access_type(ctx, ACCESS_INT);
- t0 = tcg_temp_new();
- gen_addr_reg_index(ctx, t0);
- t1 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t1, cpu_xer);
- tcg_gen_andi_i32(t1, t1, 0x7F);
- t2 = tcg_constant_i32(rS(ctx->opcode));
- gen_helper_stsw(tcg_env, t0, t1, t2);
-}
#if !defined(CONFIG_USER_ONLY)
static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
@@ -4940,10 +4842,6 @@ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000,
PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
-GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
-GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
-GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
/* ISA v3.0 changed the extended opcode from 62 to 30 */
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
#if defined(TARGET_PPC64)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 26b308e435..76b1011fad 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -585,6 +585,109 @@ TRANS(CRANDC, cr_logic_common, tcg_gen_andc_i32);
TRANS(CREQV, cr_logic_common, tcg_gen_eqv_i32);
TRANS(CRORC, cr_logic_common, tcg_gen_orc_i32);
+
+/*** Integer load and store strings ***/
+
+/* lswi */
+static bool trans_LSWI(DisasContext *ctx, arg_LSWI *a)
+{
+ TCGv t0;
+ TCGv_i32 t1, t2;
+ int nb = a->rb;
+ int start = a->rt;
+ int ra = a->ra;
+ int nr;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return true;
+ }
+ if (nb == 0) {
+ nb = 32;
+ }
+ nr = DIV_ROUND_UP(nb, 4);
+ if (unlikely(lsw_reg_in_range(start, nr, ra))) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
+ return true;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ t0 = tcg_temp_new();
+ gen_addr_register(ctx, t0);
+ t1 = tcg_constant_i32(nb);
+ t2 = tcg_constant_i32(start);
+ gen_helper_LSW(tcg_env, t0, t1, t2);
+
+ return true;
+}
+
+/* lswx */
+static bool trans_LSWX(DisasContext *ctx, arg_LSWX *a)
+{
+ TCGv t0;
+ TCGv_i32 t1, t2, t3;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return true;
+ }
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ t0 = tcg_temp_new();
+ gen_addr_reg_index(ctx, t0);
+ t1 = tcg_constant_i32(a->rt);
+ t2 = tcg_constant_i32(a->ra);
+ t3 = tcg_constant_i32(a->rb);
+ gen_helper_LSWX(tcg_env, t0, t1, t2, t3);
+
+ return true;
+}
+
+/* stswi */
+static bool trans_STSWI(DisasContext *ctx, arg_STSWI *a)
+{
+ TCGv t0;
+ TCGv_i32 t1, t2;
+ int nb = a->rb;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return true;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ t0 = tcg_temp_new();
+ gen_addr_register(ctx, t0);
+ if (nb == 0) {
+ nb = 32;
+ }
+ t1 = tcg_constant_i32(nb);
+ t2 = tcg_constant_i32(a->rt);
+ gen_helper_STSW(tcg_env, t0, t1, t2);
+
+ return true;
+}
+
+/* stswx */
+static bool trans_STSWX(DisasContext *ctx, arg_STSWX *a)
+{
+ TCGv t0;
+ TCGv_i32 t1, t2;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return true;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ t0 = tcg_temp_new();
+ gen_addr_reg_index(ctx, t0);
+ t1 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t1, cpu_xer);
+ tcg_gen_andi_i32(t1, t1, 0x7F);
+ t2 = tcg_constant_i32(a->rt);
+ gen_helper_STSW(tcg_env, t0, t1, t2);
+
+ return true;
+}
+
static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca,
bool compute_ov, bool compute_rc0)
{
--
2.53.0
