Prepare the Aspeed SoC model for future platforms that may contain multiple SRAM regions with different sizes and MMIO mappings.
The current implementation stores SRAM size information in a single sram_size field, which limits extensibility when additional SRAM instances are introduced. Convert sram_size into an array-based definition and update all existing users to reference sram_size[0]. This aligns with the previous SRAM MemoryRegion array conversion and provides a scalable foundation for supporting multiple SRAM regions in future SoCs. No functional change. Signed-off-by: Jamin Lin <[email protected]> --- include/hw/arm/aspeed_soc.h | 2 +- hw/arm/aspeed_ast10x0.c | 8 ++++---- hw/arm/aspeed_ast2400.c | 6 +++--- hw/arm/aspeed_ast2600.c | 4 ++-- hw/arm/aspeed_ast27x0.c | 8 ++++---- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index e6942b2936..3a7db959a9 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -172,7 +172,7 @@ struct AspeedSoCClass { /** valid_cpu_types: NULL terminated array of a single CPU type. */ const char * const *valid_cpu_types; uint32_t silicon_rev; - uint64_t sram_size; + uint64_t sram_size[ASPEED_SRAM_NUM]; uint64_t secsram_size; int pcie_num; int spis_num; diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 3e478f7520..9e597a75ec 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -240,8 +240,8 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp) /* Internal SRAM */ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(a->armv7m.cpu)->cpu_index); - memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, sc->sram_size, - &err); + memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, + sc->sram_size[0], &err); if (err != NULL) { error_propagate(errp, err); return false; @@ -493,7 +493,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data) sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST1030_A1_SILICON_REV; - sc->sram_size = 0xc0000; + sc->sram_size[0] = 0xc0000; sc->secsram_size = 0x40000; /* 256 * KiB */ sc->spis_num = 2; sc->ehcis_num = 0; @@ -521,7 +521,7 @@ static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *data) sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST1060_A2_SILICON_REV; - sc->sram_size = 0xc0000; + sc->sram_size[0] = 0xc0000; sc->secsram_size = 0x40000; /* 256 * KiB */ sc->spis_num = 2; sc->wdts_num = 4; diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index d79aa832f3..c4e5388999 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -282,7 +282,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) /* SRAM */ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, - sc->sram_size, errp)) { + sc->sram_size[0], errp)) { return; } memory_region_add_subregion(s->memory, @@ -533,7 +533,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *data) sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2400_A1_SILICON_REV; - sc->sram_size = 0x8000; + sc->sram_size[0] = 0x8000; sc->spis_num = 1; sc->ehcis_num = 1; sc->wdts_num = 2; @@ -560,7 +560,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, const void *data) sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2500_A1_SILICON_REV; - sc->sram_size = 0x9000; + sc->sram_size[0] = 0x9000; sc->spis_num = 2; sc->ehcis_num = 2; sc->wdts_num = 3; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index a69103de89..2f8f49a376 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -438,7 +438,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) /* SRAM */ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, - sc->sram_size, errp)) { + sc->sram_size[0], errp)) { return; } memory_region_add_subregion(s->memory, @@ -764,7 +764,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, const void *data) sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2600_A3_SILICON_REV; - sc->sram_size = 0x16400; + sc->sram_size[0] = 0x16400; sc->spis_num = 2; sc->ehcis_num = 2; sc->wdts_num = 4; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 0fb5e4b24c..30883ea7ce 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -778,8 +778,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) /* SRAM */ name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); - if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name, sc->sram_size, - errp)) { + if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name, + sc->sram_size[0], errp)) { return; } memory_region_add_subregion(s->memory, @@ -1151,7 +1151,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data) sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2700_A1_SILICON_REV; - sc->sram_size = 0x20000; + sc->sram_size[0] = 0x20000; sc->pcie_num = 3; sc->spis_num = 3; sc->sgpio_num = 2; @@ -1181,7 +1181,7 @@ static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const void *data) sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2700_A2_SILICON_REV; - sc->sram_size = 0x20000; + sc->sram_size[0] = 0x20000; sc->pcie_num = 3; sc->spis_num = 3; sc->sgpio_num = 2; -- 2.43.0
