On 5/25/26 07:30, Jamin Lin wrote:
This series introduces the initial ASPEED AST1040 support for QEMU.
AST1040 is the next-generation bridge/BIC controller platform
following AST1030 and is based on an ARM Cortex-M4F CPU core.
Since QEMU currently does not provide Cortex-M4F support, the
existing Cortex-M4 CPU model is used temporarily.
The current implementation provides enough functionality to boot
basic firmware environments with UART console support, HyperRAM/SRAM
mapping, and NVIC interrupt handling.
Currently this series is able to boot Zephyr successfully to the
shell prompt:
uart:~$
Example command line:
./build/qemu-system-arm \
-machine ast1040-evb \
-kernel <zephyr.elf> \
-serial mon:stdio \
-snapshot \
-nographic
There are many different types of RAM, including DRAM, SRAM, SDRAM, PSRAM,
SECSRAM, and HyperRAM. To support these memory types, we need to introduce
distinct variable names for their memory regions and memory sizes.
In addition, the SoC contains multiple SRAM instances. To make the code more
flexible and maintainable, I am considering changing the array structure to
support internal memory types such as SRAM, SDRAM, PSRAM, HyperRAM, and SECSRAM.
For example:
sram[NUM]
sram_size[NUM]
ASPEED_DEV_SRAMX
v1:
- AST1040 silicon revision ID
- SDRAM support in the Aspeed SoC framework
- Initial AST1040 SoC model
- AST1040 EVB machine model
v2:
- Add AST1040 functional test
- Add AST1040 documentation
- Convert SRAM MemoryRegion to array type
- Convert SRAM size definition to array type
Jamin Lin (9):
hw/arm/aspeed: Convert SRAM MemoryRegion to array type
hw/arm/aspeed: Convert SRAM size definition to array type
hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support
hw/arm/aspeed: Consolidate secure SRAM into SRAM array
hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID
hw/arm/aspeed: Introduce AST1040 A0 SoC model
hw/arm/aspeed: Add AST1040 EVB machine model
tests/function/aspeed: Add AST1040 functional test
docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board
docs/system/arm/aspeed.rst | 18 +-
include/hw/arm/aspeed_soc.h | 11 +-
include/hw/misc/aspeed_scu.h | 1 +
hw/arm/aspeed_ast1040.c | 254 ++++++++++++++++++++
hw/arm/aspeed_ast1040_evb.c | 73 ++++++
hw/arm/aspeed_ast10x0.c | 29 ++-
hw/arm/aspeed_ast2400.c | 14 +-
hw/arm/aspeed_ast2600.c | 10 +-
hw/arm/aspeed_ast27x0-ssp.c | 4 +-
hw/arm/aspeed_ast27x0-tsp.c | 4 +-
hw/arm/aspeed_ast27x0.c | 12 +-
hw/misc/aspeed_scu.c | 1 +
hw/arm/meson.build | 4 +-
tests/functional/arm/meson.build | 1 +
tests/functional/arm/test_aspeed_ast1040.py | 35 +++
15 files changed, 424 insertions(+), 47 deletions(-)
create mode 100644 hw/arm/aspeed_ast1040.c
create mode 100644 hw/arm/aspeed_ast1040_evb.c
create mode 100644 tests/functional/arm/test_aspeed_ast1040.py
For the series,
Reviewed-by: Cédric Le Goater <[email protected]>
Thanks,
C.
