On 17.04.2026 11:03, Anton Blanchard wrote:
Widening reductions read vs2 as a vector of SEW elements and vs1[0] as a
scalar of 2*SEW. The ISA does not allow the same vector register to be read
with different EEWs, so they must not overlap.
vs1 is read as a scalar from element 0, so it is treated as a single vector
register (independent of LMUL) when checking overlap.
Signed-off-by: Anton Blanchard <[email protected]>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 4df9a40b44..d9a0027e0b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3062,6 +3062,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
{
return reduction_check(s, a) && (s->sew < MO_64) &&
+ !is_overlapped(a->rs1, 1, a->rs2, 1 << MAX(s->lmul, 0)) &&
((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
}
Shouldn't this change be in stable qemu series?
Or is it not important there?
I'm picking it up, please let me know if I shouldn't.
Thanks,
/mjt
