[PATCH v11 03/12] target/riscv: Assert PTE.N/PBMT bits are not expected on RV32

[Philippe Mathieu-Daudé]

PTE_N and PTE_PBMT are undefined on RV64, assert we are not
under RV32.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
 target/riscv/cpu_helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 17305e1bb75..f86bfdb32e7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1490,6 +1490,7 @@ static int get_physical_address(CPURISCVState *env, 
hwaddr *physical,
         return TRANSLATE_FAIL;
     }
     if (!pbmte && (pte & PTE_PBMT)) {
+        assert(riscv_cpu_sxl(env) != MXL_RV32);
         /* Reserved without Svpbmt. */
         qemu_log_mask(LOG_GUEST_ERROR, "%s: PBMT bits set in PTE, "
                       "and Svpbmt extension is disabled: "
@@ -1643,6 +1644,7 @@ static int get_physical_address(CPURISCVState *env, 
hwaddr *physical,
     target_ulong vpn = addr >> PGSHIFT;
 
     if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
+        assert(riscv_cpu_sxl(env) != MXL_RV32);
         napot_bits = ctzl(ppn) + 1;
         if ((i != (levels - 1)) || (napot_bits != 4)) {
             return TRANSLATE_FAIL;
-- 
2.53.0