[PATCH v11 07/12] hw/riscv/boot: Rewrite setup_rom_reset_vec() using load/store API

[Philippe Mathieu-Daudé]

In order to make the following commits easier to review, do
not pre-initialize the reset_vec[] array, fill each word one
by one. Set the start and FDT load addresses using the load/
store APIs.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
 hw/riscv/boot.c | 53 ++++++++++++++++++++++---------------------------
 1 file changed, 24 insertions(+), 29 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index ae2f86c7ceb..c6ab1cc8cfb 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -18,6 +18,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/bswap.h"
 #include "qemu/datadir.h"
 #include "qemu/units.h"
 #include "qemu/error-report.h"
@@ -444,6 +445,9 @@ void riscv_rom_copy_firmware_info(MachineState *machine,
                            &address_space_memory);
 }
 
+#define CODE_WORDS 6
+#define DATA_WORDS 4
+
 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState 
*harts,
                                hwaddr start_addr,
                                hwaddr rom_base, hwaddr rom_size,
@@ -451,43 +455,34 @@ void riscv_setup_rom_reset_vec(MachineState *machine, 
RISCVHartArrayState *harts
                                uint64_t fdt_load_addr)
 {
     int i;
-    uint32_t start_addr_hi32 = 0x00000000;
-    uint32_t fdt_load_addr_hi32 = 0x00000000;
+    const bool rv32 = riscv_is_32bit(harts);
+    uint32_t reset_vec[CODE_WORDS + DATA_WORDS];
 
-    if (!riscv_is_32bit(harts)) {
-        start_addr_hi32 = start_addr >> 32;
-        fdt_load_addr_hi32 = fdt_load_addr >> 32;
-    }
-    /* reset vector */
-    uint32_t reset_vec[10] = {
-        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
-        0x02828613,                  /*     addi   a2, t0, %pcrel_lo(1b) */
-        0xf1402573,                  /*     csrr   a0, mhartid  */
-        0,
-        0,
-        0x00028067,                  /*     jr     t0 */
-        start_addr,                  /* start: .dword */
-        start_addr_hi32,
-        fdt_load_addr,               /* fdt_laddr: .dword */
-        fdt_load_addr_hi32,
-                                     /* fw_dyn: */
-    };
-    if (riscv_is_32bit(harts)) {
-        reset_vec[3] = 0x0202a583;   /*     lw     a1, 32(t0) */
-        reset_vec[4] = 0x0182a283;   /*     lw     t0, 24(t0) */
+    /* .text */
+    reset_vec[0] = 0x00000297;                  /* 1:  auipc  t0, 
%pcrel_hi(fw_dyn) */
+    reset_vec[1] = 0x02828613;                  /*     addi   a2, t0, 
%pcrel_lo(1b) */
+    if (harts->harts[0].cfg.ext_zicsr) {
+        reset_vec[2] = 0xf1402573;              /*     csrr   a0, mhartid  */
     } else {
-        reset_vec[3] = 0x0202b583;   /*     ld     a1, 32(t0) */
-        reset_vec[4] = 0x0182b283;   /*     ld     t0, 24(t0) */
-    }
-
-    if (!harts->harts[0].cfg.ext_zicsr) {
         /*
          * The Zicsr extension has been disabled, so let's ensure we don't
          * run the CSR instruction. Let's fill the address with a non
          * compressed nop.
          */
-        reset_vec[2] = 0x00000013;   /*     addi   x0, x0, 0 */
+        reset_vec[2] = 0x00000013;              /*     addi   x0, x0, 0 */
     }
+    if (rv32) {
+        reset_vec[3] = 0x0202a583;              /*     lw     a1, 32(t0) */
+        reset_vec[4] = 0x0182a283;              /*     lw     t0, 24(t0) */
+    } else {
+        reset_vec[3] = 0x0202b583;              /*     ld     a1, 32(t0) */
+        reset_vec[4] = 0x0182b283;              /*     ld     t0, 24(t0) */
+    }
+    reset_vec[5] = 0x00028067;                  /*     jr     t0 */
+
+    /* .data */
+    stq_p(&reset_vec[6], start_addr);           /* start:       .dword */
+    stq_p(&reset_vec[8], fdt_load_addr);        /* fdt_laddr:   .dword */
 
     /* copy in the reset vector in little_endian byte order */
     for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
-- 
2.53.0