On Mon, 18 May 2026 at 18:49, Richard Henderson <[email protected]> wrote: > > Compare and branch instructions, with various operand widths. > > Signed-off-by: Richard Henderson <[email protected]> > --- > target/arm/tcg/translate-a64.c | 42 ++++++++++++++++++++++++++++++++++ > target/arm/tcg/a64.decode | 9 ++++++++ > 2 files changed, 51 insertions(+) > > diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c > index 9a27c4c6ec..293aa43cc9 100644 > --- a/target/arm/tcg/translate-a64.c > +++ b/target/arm/tcg/translate-a64.c > @@ -1774,6 +1774,48 @@ static bool trans_B_cond(DisasContext *s, arg_B_cond > *a) > return true; > } > > +static bool trans_CB_cond(DisasContext *s, arg_CB_cond *a) > +{ > + static const TCGCond cb_cond[8] = { > + [0] = TCG_COND_GT, > + [1] = TCG_COND_GE, > + [2] = TCG_COND_GTU, > + [3] = TCG_COND_GEU, > + [4] = TCG_COND_NEVER, /* reserved */ > + [5] = TCG_COND_NEVER, /* reserved */ > + [6] = TCG_COND_EQ, > + [7] = TCG_COND_NE, > + }; > + TCGCond cond = cb_cond[a->cc]; > + TCGv_i64 t, m; > + > + if (!dc_isar_feature(aa64_cmpbr, s) || cond == TCG_COND_NEVER) { > + return false; > + } > + > + t = cpu_reg(s, a->rt); > + m = cpu_reg(s, a->rm); > + if (a->esz != MO_64) { > + MemOp mop = a->esz | (is_signed_cond(cond) ? MO_SIGN : 0); > + TCGv_i64 tt = tcg_temp_new_i64(); > + TCGv_i64 tm = tcg_temp_new_i64(); > + > + tcg_gen_ext_i64(tt, t, mop); > + tcg_gen_ext_i64(tm, m, mop); > + t = tt; > + m = tm; > + } > + > + reset_btype(s); > + DisasLabel match = gen_disas_label(s);
Variable declaration needs to go at top of function. Otherwise Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
