On Mon, 18 May 2026 at 18:49, Richard Henderson
<[email protected]> wrote:
>
> Signed-off-by: Richard Henderson <[email protected]>
> ---
> target/arm/tcg/translate-a64.c | 41 ++++++++++++++++++++++++++++++++++
> target/arm/tcg/a64.decode | 2 ++
> 2 files changed, 43 insertions(+)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 293aa43cc9..c4a016f36c 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -1816,6 +1816,47 @@ static bool trans_CB_cond(DisasContext *s, arg_CB_cond
> *a)
> return true;
> }
>
> +static bool trans_CB_cond_imm(DisasContext *s, arg_CB_cond_imm *a)
> +{
> + static const TCGCond cb_cond[8] = {
> + [0] = TCG_COND_GT,
> + [1] = TCG_COND_LT,
> + [2] = TCG_COND_GTU,
> + [3] = TCG_COND_LTU,
> + [4] = TCG_COND_NEVER, /* reserved */
> + [5] = TCG_COND_NEVER, /* reserved */
> + [6] = TCG_COND_EQ,
> + [7] = TCG_COND_NE,
> + };
Maybe worth a brief comment
/* Note that CB imm and CB encode the condition differently */
?
> + TCGCond cond = cb_cond[a->cc];
> + TCGv_i64 t;
> +
> + if (!dc_isar_feature(aa64_cmpbr, s) || cond == TCG_COND_NEVER) {
> + return false;
> + }
> +
> + t = cpu_reg(s, a->rt);
> + if (!a->sf) {
> + TCGv_i64 tt = tcg_temp_new_i64();
> +
> + if (is_signed_cond(cond)) {
> + tcg_gen_ext32s_i64(tt, t);
> + } else {
> + tcg_gen_ext32u_i64(tt, t);
> + }
> + t = tt;
> + }
> +
> + reset_btype(s);
> + DisasLabel match = gen_disas_label(s);
Var decl at top of function.
> +
> + tcg_gen_brcondi_i64(cond, t, a->imm6, match.label);
> + gen_goto_tb(s, 0, 4);
> + set_disas_label(s, match);
> + gen_goto_tb(s, 1, a->imm9);
> + return true;
> +}
Otherwise
Reviewed-by: Peter Maydell <[email protected]>
thanks
-- PMM
