Re: [PATCH 2/5] target/arm: Setup new registers for GPC3

[Richard Henderson]

On 5/28/26 08:34, Jim MacArthur wrote:

Adds GPCBW_EL3. A custom write function is necessary to flush TLBs
when this register is written. Also allows write to the GPCBW bit of
GPCCR_EL3.

Signed-off-by: Jim MacArthur <jim.macart...@linaro.org>
---
  target/arm/cpu.h    |  7 +++++++
  target/arm/helper.c | 19 +++++++++++++++++++
  2 files changed, 26 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 85552b573c..9944dc9727 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -546,6 +546,7 @@ typedef struct CPUArchState {
          /* RME registers */
          uint64_t gpccr_el3;
          uint64_t gptbr_el3;
+        uint64_t gpcbw_el3;
          uint64_t mfar_el3;

/* NV2 register */

@@ -1228,6 +1229,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cpu);
  typedef struct ARMGranuleProtectionConfig {
      /* GPCCR_EL3 */
      uint64_t gpccr;
+    /* GPCBW_EL3 */
+    uint64_t gpcbw;
      /* GPTBR_EL3 */
      uint64_t gptbr;
      /* ID_AA64MMFR0_EL1.PARange */
@@ -2098,6 +2101,10 @@ FIELD(GPCCR, NA6, 27, 1)
  FIELD(GPCCR, NA7, 28, 1)
  FIELD(GPCCR, GPCBW, 29, 1)

+FIELD(GPCBW, BWSIZE, 37, 2)

+FIELD(GPCBW, BWSTRIDE, 32, 5)
+FIELD(GPCBW, BWADDR, 0, 25)
+
  FIELD(MFAR, FPA, 12, 40)
  FIELD(MFAR, NSE, 62, 1)
  FIELD(MFAR, NS, 63, 1)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 34487eeaa3..12453fe39f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4990,6 +4990,10 @@ static void gpccr_write(CPUARMState *env, const 
ARMCPRegInfo *ri,
                     R_GPCCR_SPAD_MASK | R_GPCCR_NSPAD_MASK | 
R_GPCCR_RLPAD_MASK;
      }

+ if (cpu_isar_feature(aa64_rme_gpc3 , env_archcpu(env))) {

+        rw_mask |= R_GPCCR_GPCBW_MASK;
+    }
+
      env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & 
~rw_mask);
  }

@@ -4999,11 +5003,26 @@ static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri)

                                       env_archcpu(env)->reset_l0gptsz);
  }

+static void gpcbw_write(CPUARMState *env, const ARMCPRegInfo *ri,

+                        uint64_t value)
+{
+    uint64_t rw_mask = R_GPCBW_BWADDR_MASK | R_GPCBW_BWSTRIDE_MASK |
+                       R_GPCBW_BWSIZE_MASK;
+    ARMCPU *cpu = env_archcpu(env);
+    tlb_flush_by_mmuidx(CPU(cpu), alle1_tlbmask(env));
+
+    env->cp15.gpcbw_el3 = (value & rw_mask) | (env->cp15.gpcbw_el3 & ~rw_mask);

There's no need to merge, because all other fields are RES0.
Just value & rw_mask is sufficient.

This is true for GPCCR too, fwiw, but fixing that as a separate patch.


r~