On 5/27/2026 1:13 PM, Philippe Mathieu-Daudé wrote: > v11: > - rewrite some patches while reviewing for mainstream integration > > v10 cover from Djordje: > > Hi all, > > This series adds big-endian data support for RISC-V system emulation. > > Following the discussion on previous versions, this series models > fixed-endian harts, not a mixed-endian implementation where software can > toggle MBE/SBE/UBE at runtime. The reset value of MBE/SBE/UBE is selected > from the CPU configuration. These bits remain outside the > mstatus/mstatush/sstatus writable masks, so they are effectively hardwired > to 0 for the default little-endian CPUs and to 1 when `big-endian=on`. > > The user-visible `big-endian` CPU property is exposed only after the data > path, boot path, and page-table walk support are in place, so the series > remains bisectable. > > Djordje Todorovic (6): > target/riscv: Implement runtime data endianness via MSTATUS bits > target/riscv: Fix page table walk endianness for big-endian harts > target/riscv: Add big-endian CPU configuration field and reset logic > hw/riscv/boot: Honour data endianness > target/riscv: Expose and document the CPU 'big-endian' property > tests/functional: Add RISC-V endianness test > > Philippe Mathieu-Daudé (6): > target/riscv: Initialize DisasContext::mo_endian once > target/riscv: Assert PTE.N/PBMT bits are not expected on RV32 > target/riscv: De-indent some code in get_physical_address() > target/riscv: Remove target_ulong use in get_physical_address() > hw/riscv/boot: Rewrite setup_rom_reset_vec() using load/store API > hw/riscv/boot: Replace cpu_to_le32() -> const_le32() > > docs/system/target-riscv.rst | 29 ++++++ > target/riscv/cpu.h | 1 + > target/riscv/internals.h | 29 ++++-- > target/riscv/cpu_cfg_fields.h.inc | 1 + > hw/riscv/boot.c | 93 ++++++++++--------- > target/riscv/cpu.c | 15 ++- > target/riscv/cpu_helper.c | 44 +++++---- > target/riscv/tcg/tcg-cpu.c | 2 + > target/riscv/translate.c | 22 ++--- > target/riscv/insn_trans/trans_rva.c.inc | 4 +- > target/riscv/insn_trans/trans_rvd.c.inc | 4 +- > target/riscv/insn_trans/trans_rvf.c.inc | 4 +- > target/riscv/insn_trans/trans_rvi.c.inc | 8 +- > target/riscv/insn_trans/trans_rvzacas.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzalasr.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 +- > target/riscv/insn_trans/trans_xmips.c.inc | 8 +- > target/riscv/insn_trans/trans_xthead.c.inc | 16 ++-- > target/riscv/insn_trans/trans_zilsd.c.inc | 4 +- > tests/functional/riscv64/meson.build | 1 + > tests/functional/riscv64/test_endianness.py | 57 ++++++++++++ > 23 files changed, 240 insertions(+), 122 deletions(-) > create mode 100644 tests/functional/riscv64/test_endianness.py >
Seems there are some build failures: https://github.com/p-b-o/qemu-ci/actions/runs/26537039673 Regards, Pierrick
