On Thu, May 28, 2026 at 6:16 AM Philippe Mathieu-Daudé <[email protected]> wrote: > > From: Djordje Todorovic <[email protected]> > > Add functional test for the RISC-V 'big-endian' CPU property. > > Signed-off-by: Djordje Todorovic <[email protected]> > Reviewed-by: Thomas Huth <[email protected]> > Reviewed-by: Philippe Mathieu-Daudé <[email protected]> > Tested-by: Philippe Mathieu-Daudé <[email protected]> > Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > tests/functional/riscv64/meson.build | 1 + > tests/functional/riscv64/test_endianness.py | 57 +++++++++++++++++++++ > 2 files changed, 58 insertions(+) > create mode 100644 tests/functional/riscv64/test_endianness.py > > diff --git a/tests/functional/riscv64/meson.build > b/tests/functional/riscv64/meson.build > index b996c89d7df..5871211e899 100644 > --- a/tests/functional/riscv64/meson.build > +++ b/tests/functional/riscv64/meson.build > @@ -11,6 +11,7 @@ tests_riscv64_system_quick = [ > ] > > tests_riscv64_system_thorough = [ > + 'endianness', > 'boston', > 'sifive_u', > 'tuxrun', > diff --git a/tests/functional/riscv64/test_endianness.py > b/tests/functional/riscv64/test_endianness.py > new file mode 100644 > index 00000000000..9e0b3b7db5c > --- /dev/null > +++ b/tests/functional/riscv64/test_endianness.py > @@ -0,0 +1,57 @@ > +#!/usr/bin/env python3 > +# > +# Functional tests for RISC-V big-endian support > +# > +# Copyright (c) 2026 MIPS > +# > +# SPDX-License-Identifier: GPL-2.0-or-later > + > +from qemu_test import QemuSystemTest, Asset > +from qemu_test import wait_for_console_pattern > + > + > +class RiscvBigEndian(QemuSystemTest): > + """ > + Tests for RISC-V runtime big-endian data support. > + > + Uses a bare-metal RV64 ELF that detects data endianness at runtime > + by storing a 32-bit word and reading back byte 0. Prints "ENDIAN: BE" > + or "ENDIAN: LE" to the NS16550A UART on the virt machine. > + """ > + > + timeout = 10 > + > + ASSET_BE_TEST = Asset( > + 'https://github.com/MIPS/linux-test-downloads/raw/main/' > + 'riscvbe-baremetal/be-test-bare-metal.elf', > + '9ad51b675e101de65908fadbac064ed1d0564c17463715d09dd734db86ea0f58') > + > + def _run_bare_metal(self, big_endian=False): > + self.set_machine('virt') > + kernel = self.ASSET_BE_TEST.fetch() > + self.vm.add_args('-bios', 'none') > + self.vm.add_args('-kernel', kernel) > + if big_endian: > + self.vm.add_args('-cpu', 'rv64,big-endian=on') > + self.vm.set_console() > + self.vm.launch() > + expected = 'ENDIAN: BE' if big_endian else 'ENDIAN: LE' > + wait_for_console_pattern(self, expected) > + > + def test_bare_metal_littleendian(self): > + """ > + Boot bare-metal ELF on virt with default little-endian CPU. > + Expects "ENDIAN: LE" on UART. > + """ > + self._run_bare_metal(big_endian=False) > + > + def test_bare_metal_bigendian(self): > + """ > + Boot bare-metal ELF on virt with big-endian=on CPU property. > + Expects "ENDIAN: BE" on UART. > + """ > + self._run_bare_metal(big_endian=True) > + > + > +if __name__ == '__main__': > + QemuSystemTest.main() > -- > 2.53.0 > >
