Align all the CSR values. mcountinhibit is the longest CSR name at 13 characters, so use that width for PC, implicit state, and CSR names. Also remove the redundant '=' from the implicit state lines.t
Signed-off-by: Anton Blanchard <[email protected]> --- target/riscv/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) This makes it easier to read the output in my eyes, but I wasn't sure if the format is set in stone. Feel free to drop it if so. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b38ddc39ea..883aa906a1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -575,7 +575,7 @@ static void riscv_dump_csr(CPURISCVState *env, int csrno, FILE *f) * to do the filtering of the registers that are present. */ if (res == RISCV_EXCP_NONE) { - qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + qemu_fprintf(f, " %-13s " TARGET_FMT_lx "\n", csr_ops[csrno].name, val); } } @@ -604,17 +604,17 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) uint8_t *p; #if !defined(CONFIG_USER_ONLY) - qemu_fprintf(f, " %s %s\n", "priv = ", riscv_priv_str(env->priv)); + qemu_fprintf(f, " %-13s %s\n", "priv", riscv_priv_str(env->priv)); if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); + qemu_fprintf(f, " %-13s %d\n", "V", env->virt_enabled); } if (cpu->cfg.ext_zicfilp) { - qemu_fprintf(f, " %s %d\n", "elp = ", env->elp); + qemu_fprintf(f, " %-13s %d\n", "elp", env->elp); } #endif - qemu_fprintf(f, " %s %" PRIx64 "\n", "pc ", env->pc); + qemu_fprintf(f, " %-13s %" PRIx64 "\n", "pc", env->pc); #ifndef CONFIG_USER_ONLY for (i = 0; i < ARRAY_SIZE(csr_ops); i++) { int csrno = i; -- 2.34.1
