We support the fw_cfg device on more architectures and machines that
we let on about in the documentation. Luckily most of the new ones
(notably riscv and loongarch) have followed the straightforward layout
that the Arm virt board picked. Allowing every machine type to have
its own special-snowflake register layout has no particular benefits
and tends to result in guest OSes accumulating ifdef ladders to deal
with all the unnecessary variation.
This patchset:
* updates the docs to present the arm/riscv/loongarch memory
mapped layout as the "standard" layout to be used by all
new architectures/machines in future
* adds the layouts used by various existing boards that we
didn't document (PA-RISC, SPARC, PPC and MIPS)
* tightens up fw_cfg_init_mem_dma() and fw_cfg_init_io_dma()
functions so that they don't provide flexibility to the
caller to pick their own weird new layout. None of the
callers were using this flexibility, so it's better to
have fw_cfg_init_mem_dma() give the "standard MMIO" layout
and fw_cfg_init_io_dma() give the x86 ioport layout.
thanks
-- PMM
Peter Maydell (5):
docs/specs/fw_cfg: Document all architecture register layouts
hw/nvram/fw_cfg: Enforce standard layout for fw_cfg_init_mem_dma()
hw/nvram/fw_cfg: Enforce standard layout for x86 fw_cfg I/O ports
hw/nvram/fw_cfg: Remove support for I/O port fw_cfg without DMA
hw/nvram/fw_cfg: Document fw_cfg_init_mem_nodma()
docs/specs/fw_cfg.rst | 28 ++++++++++++++++---
hw/arm/virt.c | 2 +-
hw/i386/fw_cfg.c | 3 +-
hw/i386/microvm.c | 3 +-
hw/i386/pc.c | 3 +-
hw/loongarch/fw_cfg.c | 3 +-
hw/nvram/fw_cfg.c | 22 ++++++---------
hw/riscv/virt.c | 3 +-
include/hw/nvram/fw_cfg.h | 58 +++++++++++++++++++++++++++++++++++----
9 files changed, 92 insertions(+), 33 deletions(-)
--
2.43.0
