Hello, In this version a new patch was added to include board tests. There's also minor changes in the docs to cite how the board was tested.
No other changes were made. Patches are based on alistair/riscv-to-apply.next @2d9be31092, plus Chao Liu's series "[PATCH v6 0/7] riscv: add initial sdext support" [1]. For convenience this series is available at this branch: https://gitlab.com/danielhb/qemu/-/tree/riscv-server-ref_v7 Changes from v6: - patch 4 (new): add riscv-server-ref tests - patch 5 (former 4): add more information about how the machine can be tested/run - v6 link: https://lore.kernel.org/qemu-devel/[email protected]/ Daniel Henrique Barboza (3): target/riscv/cpu.c: remove 'bare' condition for .profile tests/functional/riscv64: add riscv-server-ref tests docs: add riscv-server-ref.rst Fei Wu (2): target/riscv: Add server platform reference cpu hw/riscv: server platform reference machine configs/devices/riscv64-softmmu/default.mak | 1 + docs/system/riscv/riscv-server-ref.rst | 52 + docs/system/target-riscv.rst | 1 + hw/riscv/Kconfig | 15 + hw/riscv/meson.build | 1 + hw/riscv/server_platform_ref.c | 1373 +++++++++++++++++++ target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 12 +- tests/functional/riscv64/meson.build | 2 + tests/functional/riscv64/test_opensbi.py | 4 + tests/functional/riscv64/test_server_ref.py | 57 + 11 files changed, 1518 insertions(+), 1 deletion(-) create mode 100644 docs/system/riscv/riscv-server-ref.rst create mode 100644 hw/riscv/server_platform_ref.c create mode 100755 tests/functional/riscv64/test_server_ref.py -- 2.43.0
