在 2026-06-04四的 06:52 -0300，Daniel Henrique Barboza写道： > From: Fei Wu <[email protected]> > > The harts requirements of RISC-V server platform [1] require RVA23 > ISA > profile support and others. > > This patch provides a new "riscv-server-ref" CPU to go along with the > future "riscv-server-ref" board. > > [1] > https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc > > Signed-off-by: Fei Wu <[email protected]> > Signed-off-by: Daniel Henrique Barboza > <[email protected]> > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 11 +++++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 30dcdcfaae..a150acd151 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -42,6 +42,7 @@ > #define TYPE_RISCV_CPU_RVA22S64 > RISCV_CPU_TYPE_NAME("rva22s64") > #define TYPE_RISCV_CPU_RVA23U64 > RISCV_CPU_TYPE_NAME("rva23u64") > #define TYPE_RISCV_CPU_RVA23S64 > RISCV_CPU_TYPE_NAME("rva23s64") > +#define TYPE_RISCV_CPU_RVSERVER_REF RISCV_CPU_TYPE_NAME("riscv- > server-ref") > #define TYPE_RISCV_CPU_IBEX > RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti- > c") > #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive- > e") > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 3f0f931335..c4a5a7f1cb 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -3315,6 +3315,17 @@ static const TypeInfo riscv_cpu_type_infos[] = > { > #endif > ), > > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, > TYPE_RISCV_BARE_CPU, > + .misa_mxl_max = MXL_RV64, > + .profile = &RVA23S64, > + > + .cfg.ext_zkr = true, > + .cfg.ext_svadu = true, > + .cfg.ext_sdext = true, > + > + .cfg.max_satp_mode = VM_1_10_SV48,
Here it only declares the maximum supported SATP mode is Sv48, but the RVSP spec requires Sv48, and the RVSP REF machine created in the next patch also requires it (because the above 4G PCIe memory space is beyond 40-bit physical address space). Without `,sv48=on` explicitly enabled on the CPU, booting EDK2 firmware will fail because of the out-of-address-space PCIe memory space. Maybe a RVSERVER profile could be defined for CPUs conformant to server platform spec (because that spec really adds some requireed extensions), and use it for RVSERVER_REF CPU type? Thanks, Icenowy > + ), > + > #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, > .cfg.max_satp_mode = VM_1_10_SV57,
